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LT1468IS8 Datasheet(PDF) 10 Page - Linear Technology |
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LT1468IS8 Datasheet(HTML) 10 Page - Linear Technology |
10 / 16 page LT1468 10 1468fa APPLICATIONS INFORMATION The LT1468 may be inserted directly into many operational amplifier applications improving both DC and AC perfor- mance, provided that the nulling circuitry is removed. The suggested nulling circuit for the LT1468 is shown below. contacts to the inputs can exceed the inherent drift of the amplifier. Air currents over device leads should be minimized, package leads should be short, and the two input leads should be as close together as possible and maintained at the same temperature. Make no connection to Pin 8. This pin is used for factory trim of the inverting input current. The parallel combination of the feedback resistor and gain setting resistor on the inverting input can combine with the input capacitance to form a pole that can cause peaking or even oscillations. For feedback resistors greater than 2k, a feedback capacitor of the value: CF > (RG)(CIN/RF) should be used to cancel the input pole and optimize dy- namic performance. For applications where the DC noise gain is one, and a large feedback resistor is used, CF should be greater than or equal to CIN. An example would be a DAC I-to-V converter as shown on the front page of this data sheet where the DAC can have many tens of pF of output capacitance. Another example would be a gain of –1 with 5k resistors; a 5pF to 10pF capacitor should be added across the feedback resistor. The frequency response in a gain of –1 is shown in the Typical Performance curves with 2k and 5.1k resistors with a 5pF feedback capacitor. Offset Nulling – + LT1468 1 5 100k V– V+ 4 2.2μF 0.1μF 2.2μF 0.1μF 7 6 3 2 1468 AI01 Layout and Passive Components The LT1468 requires attention to detail in board layout in order to maximize DC and AC performance. For best AC results (for example fast settling time) use a ground plane, short lead lengths, and RF-quality bypass capacitors (0.01μF to 0.1μF) in parallel with low ESR bypass capaci- tors (1μF to 10μF tantalum). For best DC performance, use “star” grounding techniques, equalize input trace lengths and minimize leakage (i.e., 1.5GΩ of leakage between an input and a 15V supply will generate 10nA—equal to the maximum IB– specification.) Board leakage can be minimized by encircling the input circuitry with a guard ring operated at a potential close to that of the inputs. For inverting configurations tie the ring to ground, in noninverting connections tie the ring to the inverting input (note the input capacitance will increase which may require a compensating capacitor as discussed below.) Microvolt level error voltages can also be generated in the external circuitry. Thermocouple effects caused by temperature gradients across dissimilar metals at the Nulling Input Capacitance – + LT1468 1468 AI02 RG RF CIN CF VIN VOUT |
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