3

Block Diagram

High

Voltage

Level

Translator

Logic

Linear

Reg

EN

Mode

GND

Current

Sense

and

Driver

Current

Sense

and

Driver

Linear

Reg

High

Voltage

Level

Translator

Pin Description

P-channel gate voltage supply. Generated by an internal linear regulator. A 0.1µF capacitor should be connected between

Negative high voltage supply.

N-channel gate voltage supply. Generated by an internal linear regulator. A 0.1µF capacitor should be connected between

Logic supply voltage.

GND

Low voltage ground.

High voltage power ground.

Logic control input. When mode is high, logic input high turns OFF output high voltage P-Channel.

Logic control input. When mode is high, logic input high turns ON output high voltage N-Channel.

EN

Logic enable input. Logic low enables IC.

Mode

Pulse by pulse over current sensing for P-Channel MOSFET.

Pulse by pulse over current sensing for N-Channel MOSFET.

Gate drive for external P-channel MOSFET.

Gate drive for external N-channel MOSFET.

HV450