Preliminary Data Sheet: TM060

Page 6 of 48

Rev: P06

Date: 11/22/04

Recommended Operating Conditions & Electrical Characteristics

Table 3

Symbol

Parameter

Minimum

Nominal

Maximum

Units

Notes

Vdd2.5

2.5V digital power supply voltage

2.3

2.5

2.7

Volts

Vdd3.3

3.3V digital power supply voltage

3.0

3.3

3.6

Volts

AVdd2.5

2.5V analog power supply voltage

2.3

2.5

2.7

Volts

High level input voltage

2.0

-

Vdd3.3 + 0.3

Volts

2

Low level input voltage

0.3

-

0.8

Volts

2

0.9*Vdd3.3

-

-

Volts

2

-

-

0.4

Volts

2

Low level input voltage (PECL inputs)

0.86

-

2.125

Volts

High level input voltage (PECL inputs)

1.49

-

2.72

Volts

PECL differential input voltage

0.3

-

Vdd3.3

Volts

Input capacitance

-

-

10

pF

Clock fall time (TCXO, OCXO, VCXO)

-

-

5

nS

Clock rise time (TCXO, OCXO, VCXO)

-

-

5

nS

Input reference signal positive pulse width

10

-

-

nS

Input reference signal negative pulse width

10

-

nS

Operating Ambient Temperature Range

0

-

70

°C

Icc (Vdd2.5)

2.5V digital supply current

-

-

500

mA

Icc (Vdd3.3)

3.3V digital supply current

-

-

200

mA

Icc (Avdd2.5) 2.5V analog supply current

-

-

50

mA

Pd

Device power dissipation

-

-

2.0

W

Absolute Maximum Ratings

Table 2

Symbol

Parameter

Minimum

Nominal

Maximum

Units

Notes

Vdd2.5

Logic power supply voltage, 2.5V

-0.3

-

3.0

Volts

1

Vdd3.3

Logic power supply voltage 3.3V

-0.3

-

4.0

Volts

1

AVdd2.5

Analog power supply voltage, 2.5V

-0.3

-

4.0

Volts

1

Logic input voltage, rel. to GND

-0.3

-

Vdd3.3 + 0.5

Volts

1

Storage Temperature

-55

-

110

°C

1

Note 1: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum rated

conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions.

Note 2: LVTTL compatible

Register Map

Table 4

Address

Reg Name

Description

Type

0x00

Chip_ID_Low

Low byte of chip ID

R

0x01

Chip_ID_High

High byte of chip ID

R

0x02

Chip_Revision

Chip revision number

R

0x03

Bandwidth_PBO

Bandwidth & Phase Build-Out option

R/W

0x04

Ctl_Mode

Manual or automatic selection of Op_Mode, BITS clock output frequency

indication, and frame/multi-frame sync pulse width mode control

R/W

0x05

Op_Mode

Master Free Run, Locked, or Hold Over mode, or Slave mode

R/W