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IW4516BD Datasheet(PDF) 1 Page - IK Semicon Co., Ltd |
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IW4516BD Datasheet(HTML) 1 Page - IK Semicon Co., Ltd |
1 / 7 page TECHNICAL DATA IW4516B Presettable Up/Down Counter High-Voltage Silicon-Gate CMOS ORDERING INFORMATION IW4516BN Plastic IW4516BD SOIC TA = -55° to 125° C for all packages The IW4516B Presettable Binary Up/Down Counter consists of four synchronously clocked D-type flip-flops (with a gating structure to provide T-type flip-flop capability) connected as counters. This counter can be cleared by a high level on the RESET line, and can be preset to any binary number present on the jam inputs by a high level on the PRESET ENABLE line. If the CARRY-IN input is held low, the counter advances up or down on each positive-going clock transition. Synchronous cascading is accomplished by connecting all clock inputs in parallel and connecting the CARRY-OUT of a less significant stage to the CARRY-IN of a more significant stage. The IW4516B can be cascaded in the ripple mode by connecting the CARRY-OUT to the clock of the next stage. If the UP/DOWN input changes during a terminal count, the CARRY-OUT must be gated with the clock, and the UP/DOWN input must change while the clock is high. This method provides a clean clock signal to the subsequent counting stage. PIN ASSIGNMENT • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 μA at 18 V over full package- temperature range; 100 nA at 18 V and 25 °C • Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply LOGIC DIAGRAM FUNCTION TABLE Inputs Outputs CL CI U/D PE Rev. 00 R Mode X H X L L NO COUNT L H L L COUNT UP L L L L COUNT DOWN X X X H L PRESET X X X X H RESET X = don’t care PIN 16=VCC PIN 8= GND |
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