IL33197A

Figure 4. Switching Waveform W/W and INT Active

T1 Debounce Timing

The criteria for an input signal to be detected is that it should be active at two successive negative internal clock edges.

The inputs are sampled on the negative edge of the internal clock. If two consecutive samples are the same, the input is

detected as being in that state. Hence the time T1 from a signal becoming active to the time that the circuit responds can

be anytime from 4 x tb1 to 2 x 4 x tb1 (due to synchronizing the input to the oscillator period) when the oscillator is

oscillating with a time base of tb1 and 4 x tb2 to 2 x 4 x tb2, when the oscillator is oscillating with a time base of tb2.

The following table summarizes all T1 debounce timings:

Condition

Debounce Time

INT Active

INT Inactive

W/W Active When INT Inactive

W/W Active When INT Active During T3

W/W Active When INT Active During T4

Two IL33197A Devices Using One Decoupling Resistor and Capacitor

Two devices may be connected to the power source using a common R1 resistor for protection against overvoltages. If

this is done it should be noted that the current flowing through R1 is increased and hence the voltage drop across

R1 is increased.

Overvoltage Protection

In reference to the Block Diagram and Typical Application, all of the foregoing operational cases require:

R1

≥100 Ω, C1≥47 µF

R3

≥1.0 kΩ, R4≥4.7 kΩ, R5≥4.7 kΩ

The circuit will not operate during the transient conditions. By using the above component values, the circuit will

be able to sustain the following overvoltages on Vbb without permanent damage:

1. +28 V for 5 minutes

2. –15 V for 5 minutes

3. –16 V cycled off for 1.0 minute

4. +80 V pulse decaying exponentially to 8.0 V in 400 ms repeated 3 times at 1.0 minute intervals.

5.

±300 V pulse decaying exponentially to 30 V in 300 ms with a maximum energy of 1.0 Joule.

6.

±100 V pulse decaying exponentially to 10 V in 2 ms.

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