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LT1787CS8 Datasheet(PDF) 9 Page - Linear Technology |
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LT1787CS8 Datasheet(HTML) 9 Page - Linear Technology |
9 / 16 page 9 LT1787/LT1787HV 1787fc PIN FUNCTIONS FIL–, FIL+ (Pins 1, 8): Negative and Positive Filter Termi- nals. Differential mode noise can be filtered by connecting a capacitor across FIL– and FIL+. Pole frequency f–3dB = 1/(2πRC), R = 1.25kΩ. VS– (Pin 2): Negative Input Sense Terminal. Negative sense voltage will result in an output sinking current proportional to the sense current. VS– is connected to an internal gain-setting resistor RG1A and supplies bias cur- rent to the internal amplifier. DNC (Pin 3): Do Not Connect. Connected internally. Do not connect external circuitry to this pin. VEE (Pin 4): Negative Supply or Ground for Single Supply Operation. VOUT (Pin 5): Voltage Output or Current Output propor- tional to the magnitude of the sense current flowing through RSENSE. For bidirectional current sensing opera- tion, VOUT = AV • VSENSE + VOUT(O) + VBIAS, where: VOUT > VBIAS for VS+ > VS– VOUT < VBIAS for VS+ < VS– VOUT(O) is the no load output voltage at VSENSE = 0V. VBIAS (Pin 6): Output Bias Pin. For single supply, bidirec- tional current sensing operation, VBIAS is connected to an external bias voltage, so that at VSENSE = 0V, VOUT = VOUT(O) + VBIAS. For dual supply, bidirectional current sensing operation, VBIAS is connected to ground. Thus, VOUT = VOUT(O) at VSENSE = 0V. VS+ (Pin 7): Positive Input Sense Terminal. Positive sense voltage will result in an output sourcing current propor- tional to the sense current. VS+ is connected to an internal gain-setting resistor RG2A. Connecting a supply to VS+ and a load to VS– will allow the LT1787 to measure its own supply current. BLOCK DIAGRAM RSENSE 1787 F 01 RG2A 1.25k RG2B 1.25k RG1A 1.25k RG1B 1.25k VOUT IOUT VBIAS ROUT 20k VS – – + A1 Q1 Q2 CURRENT MIRROR VEE FIL– VS + FIL+ ISENSE Figure 1. LT1787 Functional Diagram |
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