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LT3500EDD-PBF Datasheet(PDF) 10 Page - Linear Technology |
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LT3500EDD-PBF Datasheet(HTML) 10 Page - Linear Technology |
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10 / 28 page  LT3500 10 3500fb OPERATION The LT3500 is a constant frequency, current mode buck converter with an internal 2.3A switch plus a linear regula- tor with 13mA output capability. Control of both outputs is achieved with a common SHDN pin, internal regulator, oscillator, undervoltage detect, soft-start, thermal shut- down and power-on reset. If the SHDN pin is taken below its 0.8V threshold, the LT3500 will be placed in a low quiescent current mode. In this mode the LT3500 typically draws 12μA from the VIN pin. When the SHDN pin is floated or driven above 0.76V, the internal bias circuits turn on generating an internal regu- lated voltage, 0.8(VFB) and 1V(RT/SYNC) references, and a POR signal which sets the soft-start latch. As the RT/SYNC pin reaches its 1V regulation point, the internal oscillator will start generating a clock signal at a frequency determined by the resistor from the RT/SYNC pin to ground. Alternatively, if a synchronization signal is detected by the LT3500 at the RT/SYNC pin, a clock signal will be generated at the incoming frequency on the rising edge of the synchronization pulse. In addition, the internal slope compensation will be automatically adjusted to pre- vent subharmonic oscillation during synchronization. The LT3500 is a constant frequency, current mode step- down converter. Current mode regulators are controlled by an internal clock and two feedback loops that control the duty cycle of the power switch. In addition to the normal error amplifier, there is a current sense amplifier that monitors switch current on a cycle-by-cycle basis. This technique means that the error amplifier commands current to be delivered to the output rather than voltage. A voltage fed system will have low phase shift up to the resonant frequency of the inductor and output capacitor, then an abrupt 180° shift will occur. The current fed system will have 90° phase shift at a much lower frequency, but will not have the additional 90° shift until well beyond the LC resonant frequency. This makes it much easier to frequency compensate the feedback loop and also gives much quicker transient response. During power up, the POR signal sets the soft-start latch, which discharges the SS pin to ensure proper start-up operation. When the SS pin voltage drops below 100mV, the VC pin is driven low disabling switching and the soft- start latch is reset. Once the latch is reset the soft-start capacitor starts to charge with a typical value of 2.75μA. As the voltage rises above 100mV on the SS pin, the VC pin will be driven high by the error amplifier. When the voltage on the VC pin exceeds 0.8V, the clock set-pulse sets the driver flip-flop which turns on the internal power NPN switch. This causes current from VIN, through the NPN switch, inductor and internal sense resistor, to increase. When the voltage drop across the internal sense resistor exceeds a predetermined level set by the voltage on the VC pin, the flip-flop is reset and the internal NPN switch is turned off. Once the switch is turned off the inductor will drive the voltage at the SW pin low until the external Schottky diode starts to conduct, decreasing the current in the inductor. The cycle is repeated with the start of each clock cycle. However, if the internal sense resistor voltage exceeds the predetermined level at the start of a clock cycle, the flip-flop will not be set resulting in a further decrease in inductor current. Since the output current is controlled by the VC voltage, output regulation is achieved by the error amplifier continually adjusting the VC pin voltage. The error amplifier is a transconductance amplifier that compares the FB voltage to either the SS pin voltage minus 100mV or an internally regulated 800mV, whichever is lowest. Compensation of the loop is easily achieved with a simple capacitor or series resistor/capacitor from the VC pin to ground. Since the SS pin is driven by a constant current source, a single capacitor on the soft-start pin will generate controlled linear ramp on the output voltage. If the current demanded by the output exceeds the maxi- mum current dictated by the VC pin clamp, the SS pin will be discharged, lowering the regulation point until the output voltage can be supported by the maximum current. When overload is removed, the output will soft-start from the overload regulation point. |
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