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LT3750EMS Datasheet(PDF) 11 Page - Linear Technology |
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LT3750EMS Datasheet(HTML) 11 Page - Linear Technology |
11 / 16 page 11 LT3750 3750fa APPLICATIO S I FOR ATIO Figure 4. Recommended Board Layout (Not to Scale) Board Layout The high voltage operation of the the LT3750 demands careful attention to board layout. Observe the following points: 1. Minimize the area of the high voltage end of the second- ary winding. 2. Provide sufficient spacing for all high voltage nodes (NMOS drain, VOUT and the secondary winding of the transformer) in order to meet breakdown voltage requirements. 3. Keep the electrical path formed by C1, the primary of T1 and drain of the NMOS as small as possible. Increasing the size of this path effectively increases the leakage inductance of T1 resulting in an overvoltage condition on the drain of the NMOS. 1 CTRANS CPRI RBG 2 3 4 5 10 LT3750 9 8 7 6 RSENSE M1 RDCM RVOUT COUT 3750 F04 DOUT T1 1:N CIN VCC VTRANS CHARGE RDONE • • + |
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