CoreSDLC

2

v4.0

General Description

The CoreSDLC macro provides a high-speed synchronous

serial

communication

controller

that

utilizes

the

synchronous data link control (SDLC) protocol. Operation

of the controller is similar to that used in the Intel

8XC152 Global Serial Channel (GSC) device working in

SDLC mode under CPU control. Communication with a

CPU is realized through the Special Function Register

(SFR) interface and three interrupt sources. This enables

interfacing CoreSDLC easily with any CPU.

CoreSDLC consists of three primary blocks, as shown in

Figure 1:

1. Receive logic – decodes and bit strips incoming

data stream, detects flags, checks CRC, and shifts

data into an internal three-byte deep receive FIFO.

The receive logic also performs address detection,

clock recovery, and frame sequencing.

2. Transmit logic – shifts data out of an internal

three-byte deep transmit FIFO, generates a CRC,

performs bit stuffing, flag insertion, and encoding

of the transmit data stream. The transmit logic

also performs frame sequencing.

3. SFR logic – provides a simple interface to an

external processor or controller.

CoreSDLC Device Requirements

CoreSDLC has been implemented in several of Actel's device families. A summary of the implementation data is listed in Table 1.

Figure 1 • CoreSDLC Block Diagram

Transmit

Receive

Shift Register

Shift Register

Address

Detection

CRC

Checker

CRC

Generator

Bit

Stripping

Bit

Stuffing

FIFO

Receive Frame

Sequencer

Transmit Frame

Sequencer

Data

txc

rxc

sfrdatai[7:0]

sfrdatao[7:0]

sfraddr[6:0]

sfrw

sfrr

tv

re

rv

FIFO

Flag

Insertion

Data

SFR

ptv

pre

prv

rxd

txd

den

Internal Signals

Data

Decoder

Data

Encoder

Clock

Recovery

Flag

Detection

Table 1 • CoreSDLC Device Utilization and Performance

Family

Cells or Tiles

Utilization

Performance

Sequential

Combinatorial

Total

Device

Total

Fusion

408

878

1286

AFS600

10%

100 MHz

ProASIC3/E

408

878

1286

A3PE600-2

10%

100 MHz

384

1337

1721

APA150-STD

28%

65 MHz

Axcelerator

400

537

577

AX125-3

47%

140 MHz

Note: Data in this table were achieved using typical synthesis and layout settings.