CoreFIR

8

v3.0

Number of Bits of Output (nbits_out)

The

FIR

Generator

supports

only

full

precision

computation. Thus, the number of bits of output is

determined by the number of input’s and coefficients’

bits for the device family as specified in Table 4 on

page 7. The number of bits of output are specified by EQ 7:

EQ 7

where ceil is the ceiling function of a floating point data.

Asymmetric FIR and Symmetric FIR

The FIR generator supports an asymmetric FIR filter only.

Symmetric FIR filters will be supported in future releases.

Embedded RAM as LUTs (coef_fixed)

The FIR Generator utilizes a switch that determines

whether to implement DA LUTs by embedded RAM

blocks or by synthesized ROM using FPGA cells. The LUTs

are implemented by synthesized ROM using FPGA cells

when coef_fixed is equal to 1. The LUTs are implemented

by embedded RAM blocks available for Axcelerator,

equal to 0. This setting may be set to 1 for a filter design

with fixed coefficients for an FPGA device with

embedded RAM such as AX, RTAX-S, APA, and PA3, since

the overhead of the DA LUT Generator overrides the

benefits of using an embedded RAM block as a LUT. The

coef_fixed configuration parameter is valid only when

the configuration parameter fpga_family is set to ax,

apa, or pa3. Refer to Table 4 on page 7 and "Appendix I:

Sample Configuration File" on page 12 for details.

Signed/Unsigned Inputs and Coefficients

(data_signed)

The

FIR

Generator

supports

signed

or

unsigned

operations. The generator supports two cases: both

input and coefficient are unsigned, or both input and

coefficient

are

signed.

It

supports

an

unsigned

implementation when the configuration parameter

data_signed is equal to 0, and a signed implementation

when the configuration parameter data_signed is equal

to 1. Refer to Table 4 on page 7 and "Appendix I: Sample

Configuration File" on page 12 for details.

System Clock Frequency (sys_clk_frq)

The FIR Generator reads in the system clock frequency via

configuration parameter sys_clk_frq. The generated

testbench assigns this frequency to its clock generation.

The generated design runs at this frequency inside the

test bench. The configuration parameter should be

specified with the unit of MHz. Refer to Table 4 on

page 7 and "Appendix I: Sample Configuration File" on

page 12 for details.

Sample Ratio (sample_ratio)

The FIR Generator supports a configuration parameter,

sample_ratio, which specifies the sampling rate against

the system clock frequency. It defines that the data

sampling rate is equal to sys_clk_frq/sample_ratio. This

parameter provides guidance to implement a folding

architecture to reduce the size of the design. The

configuration parameter sample_ratio can only be a

positive integer greater than 1. Refer to Table 4 on

page 7 and "Appendix I: Sample Configuration File" on

page 12 for details.

Module Name (module_name)

The FIR Generator supports a configuration parameter,

module_name, that specifies the name of the generated

module.

The

generated

testbench

has

the

name

<module_name>_tb. Refer to Table 4 on page 7 and

"Appendix I: Sample Configuration File" on page 12 for

details.

FPGA Family (fpga_family)

The FIR Generator supports a configuration parameter,

fpga_family, that specifies the targeted Actel FPGA

device family. The options are ax, apa, pa3, and sxa. The

option for RTAX-S is ax. The option for RTSX-S is sxa.

Refer to Table 4 on page 7 and "Appendix I: Sample

Configuration File" on page 12 for details.

Architecture Variations

The DA algorithm for FIR provides an excellent solution,

but also introduces many variations on the design

architecture due to limitations of the FPGA resource.

FIR Filter with Large Number of

Taps

As illustrated in section "FIR Filter Using Distributed

Arithmetic Algorithm" on page 3, the number of words

with ntaps. A LUT splitting method, as defined in

"Storage and Large Number of Taps" on page 5,

effectively reduces the memory usage. The CoreFIR

Generator utilizes this method to reduce the memory

usage. It usually splits the coefficients into eight or nine

taps for each LUT when embedded RAM blocks are

available.