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COREDES-SR Datasheet(PDF) 6 Page - Actel Corporation |
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COREDES-SR Datasheet(HTML) 6 Page - Actel Corporation |
6 / 12 page CoreDES 6 v4.0 Encryption To begin the process of encrypting data, the following inputs are set: 1. K[1:64] is set to the cipher key (ck1 in Figure 6) to encrypt the data. 2. D[1:64] is set to the plaintext data (d1 in Figure 6) to be encrypted. 3. ED is set to logic '1'. 4. EN is set to logic '1'. After 16 clock cycles of the EN input being held continuously at a logic '1' value, the QVAL signal will transition from logic '0' to logic '1' and remain valid for one clock cycle, indicating that valid ciphered (encrypted) data (shown as q1 in Figure 6) is available on the Q[1:64] outputs. Figure 6 • Example Encryption Sequence CLK K[1:64] D[1:64] ED EN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 cycle Q[1:64] QVAL q1 ck1 d1 Don't care Undefined |
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