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LT3756EUD-1-TRPBF Datasheet(PDF) 7 Page - Linear Technology |
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LT3756EUD-1-TRPBF Datasheet(HTML) 7 Page - Linear Technology |
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7 / 20 page  LT3756/LT3756-1 7 37561f PIN FUNCTIONS PWMOUT (Pin 1/Pin 11): Buffered Version of PWM Signal for Driving LED Load Disconnect NMOS or Level Shift. This pin also serves a protection function for the FB overvoltage condition—will toggle if the FB input is greater than the FB regulation voltage (VFB)plus60mV(typical).ThePWMOUT pin is driven from INTVCC. Use of a FET with gate cut-off voltage higher than 1V is recommended. FB (Pin 2/Pin 12): Voltage Loop Feedback Pin. FB is intended for constant-voltage regulation or for LED protec- tion/open LED detection. The internal transconductance amplifier with output VC will regulate FB to 1.25V (nominal) through the DC/DC converter. If the FB input is regulating the loop, the OPENLED pull-down is asserted. This ac- tion may signal an open LED fault. If FB is driven above the FB threshold (by an external power supply spike, for example), the OPENLED pull-down will be de-asserted and the PWMOUT pin will be driven low to protect the LEDs from an overcurrent event. Do not leave the FB pin open. If not used, connect to GND. ISN (Pin 3/Pin 13): Connection Point for the Negative Terminal of the Current Feedback Resistor. If ISN is greater than 2.9V, the LED current can be programmed by ILED = 100mV/RLED when VCTRL > 1.2V or ILED = VCTRL –100mV/(10 • RLED). Input bias current is typically 20μA. Below 3V, ISN is an input to the short-circuit protection feature that forces GATE to 0V if ISN is more than 150mV (typ) below ISP. ISP (Pin 4/Pin 14): Connection Point for the Positive Ter- minal of the Current Feedback Resistor. Input bias current for this pin is typically 30μA. ISP is an input to the short- circuit protection feature when ISP is less than 3.1V. VC (Pin 5/Pin 15): Transconductance Error Amplifier Output Pin Used to Stabilize the Voltage Loop with an RC Network. This pin is high impedance when PWM is low, a feature that stores the demand current state variable for the next PWM high transition. Connect a capacitor between this pin and GND; a resistor in series with the capacitor is recommended for fast transient response. CTRL (Pin 6/Pin 16): Current Sense Threshold Adjustment Pin. Regulating threshold VISP – VISN is 1/10th VCTRL plus an offset. CTRL linear range is from GND to 1.1V. Connect CTRL to VREF for the 100mV default threshold. Do not leave this pin open. VREF (Pin 7/Pin 1): Voltage Reference Output Pin, Typically 2V. This pin drives a resistor divider for the CTRL pin, either for analog dimming or for temperature limit/compensation of LED load. Can supply up to 100μA. PWM (Pin 8/Pin 2): A signal low turns off switcher, idles oscillator and disconnects VC pin from all internal loads. PWMOUT pin follows PWM pin. PWM has an internal pull-down resistor. If not used, connect to INTVCC. OPENLED (Pin 9/Pin 3, LT3756 Only): An open-drain pull-down on OPENLED asserts if the FB input is greater than the FB regulation threshold minus 50mV (typical). To function, the pin requires an external pull-up resistor. When the PWM input is low and the DC/DC converter is idle, the OPENLED condition is latched to the last valid state when the PWM input was high. When PWM input goes high again, the OPENLED pin will be updated. This pin may be used to report an open LED fault. SYNC (Pin 9/Pin 3, LT3756-1 Only): The SYNC pin is used to synchronize the internal oscillator to an external logic level signal. The RT resistor should be chosen to program an internal switching frequency 20% slower than the SYNC pulse frequency. Gate turn-on occurs a fixed delay after the rising edge of SYNC. For best PWM performance, the PWM rising edge should occur at least 200ns before the SYNC rising edge. Use a 50% duty cycle waveform to drive this pin. This pin replaces OPENLED on LT3756-1 option parts. If not used, tie this pin to GND. SS (Pin 10/Pin 4): Soft-Start Pin. This pin modulates oscillator frequency and compensation pin voltage (VC) clamp. The soft-start interval is set with an external capaci- tor. The pin has a 10μA (typical) pull-up current source to an internal 2.5V rail. The soft-start pin is reset to GND by an undervoltage condition (detected by SHDN/UVLO pin) or thermal limit. RT (Pin 11/Pin 5): Switching Frequency Adjustment Pin. Set the frequency using a resistor to GND (for resistor values, see the Typical Performance curve or Table 1). Do not leave the RT pin open. SHDN/UVLO (Pin 12/Pin 6): Shutdown and Undervoltage Detect Pin. An accurate 1.22V falling threshold with ex- ternally programmable hysteresis detects when power is OK to enable switching. Rising hysteresis is generated by the external resistor divider and an accurate internal 2μA (MSOP/QFN) |
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