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A1280A-1PQ176C Datasheet(PDF) 6 Page - Actel Corporation |
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A1280A-1PQ176C Datasheet(HTML) 6 Page - Actel Corporation |
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6 / 38 page  ACT ™ 2 Fam i l y FP G A s 6v4.0 and load device inputs. An additional component of the active power dissipation is the totem-pole current in CMOS transistor pairs. The net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation. E qui v a l ent C apac i t ance The power dissipated by a CMOS circuit can be expressed by the Equation 1. Power ( µW) = CEQ * VCC2 * F (1) Where: CEQ is the equivalent capacitance expressed in pF. VCC is the power supply in volts. F is the switching frequency in MHz. Equivalent capacitance is calculated by measuring ICC active at a specified frequency and voltage for each circuit component of interest. Measurements have been made over a range of frequencies at a fixed value of VCC. Equivalent capacitance is frequency independent so that the results may be used over a wide range of operating conditions. Equivalent capacitance values are shown below. C EQ Va lues f or Ac tel F PGA s Modules (CEQM)5.8 Input Buffers (CEQI) 12.9 Output Buffers (CEQO) 23.8 Routed Array Clock Buffer Loads (CEQCR)3.9 To calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known. Equation 2 shows a piece-wise linear summation over all components. Power = VCC 2 * [(m * C EQM* fm)modules +(n * CEQI* fn)inputs + (p * (CEQO+ CL) * fp)outputs + 0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1 + 0.5 * (q2 * CEQCR * fq2)routed_Clk2 + (r2 * fq2)routed_Clk2](2) Where: Fi xed Ca paci ta nce Val ues fo r Act e l FP GA s (pF ) r1 r2 Device Type routed_Clk1 routed_Clk2 A1225A 106 106.0 A1240A 134 134.2 A1280A 168 167.8 D e t e rm i n i n g A v e ra ge S w i t chi ng F re quenc y To determine the switching frequency for a design, you must have a detailed understanding of the data input values to the circuit. The following guidelines are meant to represent worst-case scenarios so that they can be generally used to predict the upper limits of power dissipation. These guidelines are as follows: m = Number of logic modules switching at fm n = Number of input buffers switching at fn p = Number of output buffers switching at fp q1 = Number of clock loads on the first routed array clock q2 = Number of clock loads on the second routed array clock r1 = Fixed capacitance due to first routed array clock r2 = Fixed capacitance due to second routed array clock CEQM = Equivalent capacitance of logic modules in pF CEQI = Equivalent capacitance of input buffers in pF CEQO = Equivalent capacitance of output buffers in pF CEQCR = Equivalent capacitance of routed array clock in pF CL = Output lead capacitance in pF fm = Average logic module switching rate in MHz fn = Average input buffer switching rate in MHz fp = Average output buffer switching rate in MHz fq1 = Average first routed array clock rate in MHz fq2 = Average second routed array clock rate in MHz Logic Modules (m) 80% of modules Inputs switching (n) # inputs/4 Outputs switching (p) # outputs/4 First routed array clock loads (q1) 40%of sequential modules Second routed array clock loads (q2) 40%of sequential modules Load capacitance (CL) 35 pF Average logic module switching rate (fm)F/10 Average input switching rate (fn)F/5 Average output switching rate (fp)F/10 Average first routed array clock rate (fq1)F Average second routed array clock rate (fq2) F/2 |
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