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COREAI-M Datasheet(PDF) 10 Page - Actel Corporation |
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COREAI-M Datasheet(HTML) 10 Page - Actel Corporation |
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10 / 25 page  CoreAI 10 v2.0 Internal CoreAI Registers The internal register address map and reset values of each APB-accessible register for CoreAI are shown in Table 9 on page 11. In the case of 8-bit APB reads and writes (APB_16BIT_DATA = 0), each PADDR[4:0] address is significant and contains the byte listed in the far right column; however, when 16-bit APB reads and writes are used (APB_16BIT_DATA = 1), PADDR[4:1] addresses contain one 16-bit word, where each two adjacent rows in Table 9 on page 11 contain the low-order and high- order bytes, consecutively (PADDR[0] is unused in this case). Table 10 on page 12 through Table 31 on page 17 describe the various APB-accessible registers within CoreAI. Unless otherwise stated, each register can be read from or written to by an internal or external microprocessor/microcontroller. All registers are listed assuming 8-bit APB reads and writes; if 16-bit APB reads and writes are used, add 8 to each item in the "Bits" column for high-order bytes (Table 11 on page 12, Table 15 on page 13, Table 17 on page 13, Table 19 on page 14, Table 21 on page 14, Table 23 on page 14, Table 25 on page 15, Table 29 on page 16, and Table 31 on page 17). When reading from register bits that are write-only or unused (reserved), a logic 0 will be returned. When writing to register bits that are read-only or unused (reserved), no action takes place. The INTERRUPT output is generated as the logical OR of the interrupt enable bits (INTEN[14:0]) ANDed with the interrupt status bits (INT[14:0]), as shown in Figure 4. Table 7 • Settings for ATx Inputs CFG_ATx Bit-Position Values ('X' indicates "don’t care") ATx Input Usage 9 8 7 654 3 2 1 0 0 0 X X X X X X X X Temperature Monitor (default) 0 1 X X X X X X X X Digital Input 1 0 X X X X X X X X Voltage Monitor 1 1 X XXX X X X X Disabled Table 8 • Settings for Gate Driver Usage CFG_GDx Bit-Position Values ('X' indicates "don’t care") Gate Driver Usage 9 876 5 432 1 0 0 0 X X X X X X X X Register controlled (default) 1 0 XX X XXX X X Gate Driver (AGx) controlled by DDGDONx input 1 0 XX X XXX X X Reserved (unused) 1 1 X X X X X X X X Disabled (GDONx and AGx) Figure 4 • CoreAI Interrupt Logic INTEN[14] INT[14] INTEN[0] INT[0] INTERRUPT |
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