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CORE8051-AN Datasheet(PDF) 2 Page - Actel Corporation |
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CORE8051-AN Datasheet(HTML) 2 Page - Actel Corporation |
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2 / 41 page  Core8051 2 v6.0 Core Verification • Comprehensive VHDL and Verilog Testbenches • Users Can Easily Add Custom Tests by Modifying the User Testbench Using the Existing Format Contents General Description The Core8051 macro is a high-performance, single-chip, 8- bit microcontroller. It is a fully functional eight-bit embedded controller that executes all ASM51 instructions and has the same instruction set as the 80C31. Core8051 provides software and hardware interrupts, a serial port, and two timers. The Core8051 architecture eliminates redundant bus states and implements parallel execution of fetch and execution phases. Since a cycle is aligned with memory fetch when possible, most of the one-byte instructions are performed in a single cycle. Core8051 uses one clock per cycle. This leads to an average performance improvement rate of 8.0 (in terms of MIPS) with respect to the Intel device working with the same clock frequency. The original 8051 had a 12-clock architecture. A machine cycle needed 12 clocks, and most instructions were either one or two machine cycles. Therefore, the 8051 used either 12 or 24 clocks for each instruction, except for the MUL and DIV instructions. Furthermore, each cycle in the 8051 used two memory fetches. In many cases, the second fetch was a "dummy" fetch and extra clocks were wasted. Table 1 shows the speed advantage of Core8051 over the standard 8051. A speed advantage of 12 in the first column means that Core8051 performs the same instruction 12 times faster than the standard 8051. The second column in Table 1 lists the number of types of instructions that have the given speed advantage. The third column lists the total number of instructions that have the given speed advantage. The third column can be thought of as a subcategory of the second column. For example, there are two types of instructions that have a three-time speed advantage over the classic 8051, for which there are nine explicit instructions. The average speed advantage is 8.0. However, the real speed improvement seen in any system will depend on the instruction mix. Core8051 consists of the following primary blocks: • Memory Control Block – Logic that Controls Program and Data Memory • Control Processor Block – Main Controller Logic • RAM and SFR Control Block • ALU – Arithmetic Logic Unit • Reset Control Block – Provides Reset Condition Circuitry • Clock Control Block • Timer 0 and 1 Block • ISR – Interrupt Service Routine Block • Serial Port Block • Port Registers Block • PMU – Power Management Unit Block • OCI block – On-Chip Instrumentation Logic for Debug Capabilities General Description .................................................... 2 Core8051 Device Requirements ................................. 4 Core8051 Verification ................................................ 5 I/O Signal Descriptions ............................................... 5 Memory Organization ................................................ 8 Special Function Registers ........................................ 10 Instruction Set ........................................................... 11 Instruction Definitions ............................................. 19 Instruction Timing .................................................... 20 Core8051 Engine ...................................................... 27 Timers/Counters ........................................................ 28 Serial Interface .......................................................... 30 Interrupt Service Routine Unit ................................. 32 ISR Structure ............................................................. 35 Power Management Unit ........................................ 36 Power Management Implementation ..................... 36 Interface for On-Chip Instrumentation (Optional) . 37 Ordering Information .............................................. 39 List of Changes ......................................................... 40 Datasheet Categories ............................................... 40 Table 1 • Core8051 Speed Advantage Summary Speed Advantage Number of Instruction Types Number of Instructions (Opcodes) 24 1 1 12 27 83 9.6 2 2 816 38 644 89 4.8 1 2 418 31 32 9 Average: 8.0 Sum: 111 Sum: 255 |
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