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CORE8051-SR Datasheet(PDF) 6 Page - Actel Corporation |
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CORE8051-SR Datasheet(HTML) 6 Page - Actel Corporation |
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6 / 41 page  Core8051 6 v6.0 Table 5 • Core8051 Pin Description Name Type Polarity/Bus Size Description port0i Input 8 Port 0 port0o Output 8 8-bit bidirectional I/O port with separated inputs and outputs port1i Input 8 Port 1 port1o Output 8 8-bit bidirectional I/O port with separated inputs and outputs port2i Input 8 Port 2 port2o Output 8 8-bit bidirectional I/O port with separated inputs and outputs port3i Input 8 Port 3 port3o Output 8 8-bit bidirectional I/O port with separated inputs and outputs clk Input Rise Clock input for internal logic clkcpu Input Rise CPU Clock input for internal controller logic (must either be the same as the clk input or a gated version of the clk input) clkper Input Rise Peripheral Clock input for internal peripheral logic (must either be the same as the clk input or a gated version of the clk input) clkcpu_en Output High CPU Clock Enable This output may be used to optionally create a gated version of the clk input signal for connection to the clkcpu input (see "Power Management Implementation" section on page 36). clkper_en Output High Peripheral Clock Enable This output may be used to optionally create a gated version of the clk input signal for connection to the clkper input (see "Power Management Implementation" section on page 36). nreset Input Low Hardware Reset Input A logic 0 on this pin for two clock cycles while the oscillator is running resets the device. nrsto Output Low Peripheral Reset Output This globally buffered signal can be connected to logic outside Core8051 to provide an active-low asynchronous reset to peripherals. nrsto_nc Bidirectional (no-connect) Low Peripheral Reset No-Connect This signal is connected to nrsto internally and is only used by the SX-A/RTSX-S implementations, in which case it must be brought up to a top-level package pin and left unconnected at the board-level. This signal should not be used (connected) for any other device families. movx Output High Movx instruction executing On-Chip Debug Interface (Optional) TCK Input Rise JTAG test clock. If OCI is not used, connect to logic 1. TMS Input High JTAG test mode select. If OCI is not used, connect to logic 0. TDI Input High JTAG test data in. If OCI is not used, connect to logic 0. TDO Output High JTAG test data out nTRST Input Low JTAG test reset. If OCI is not used, connect to logic 1. dbgmempswr Output High Optional debug program storage write |
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