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A1280A-2VQ176I Datasheet(PDF) 5 Page - Actel Corporation |
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A1280A-2VQ176I Datasheet(HTML) 5 Page - Actel Corporation |
5 / 38 page v4.0 5 ACT ™ 2 Fam i l y FP G A s P ack ag e Th er m a l Ch ar ac t e r i st i c s The device junction to case thermal characteristic is θjc, and the junction to ambient air characteristic is θja. The thermal characteristics for θja are shown with two different air flow rates. Maximum junction temperature is 150°C. A sample calculation of the absolute maximum power dissipation allowed for a PQFP 160-pin package at commercial temperature is as follows: P o w e r D i s s ip a t io n P = [ICCstandby + ICCactive] * VCC + IOL * VOL * N + IOH * (VCC – VOH) * M Where: ICC standby is the current flowing when no inputs or outputs are changing. ICC active is the current flowing due to CMOS switching. IOL, IOH are TTL sink/source currents. VOL, VOH are TTL level output voltages. N equals the number of outputs driving TTL loads to VOL. M equals the number of outputs driving TTL loads to VOH. An accurate determination of N and M is problematical because their values depend on the family type, design details, and on the system I/O. The power can be divided into two components: static and active. S tat i c P o w e r Co m ponen t Actel FPGAs have small static power components that result in lower power dissipation than PALs or PLDs. By integrating multiple PALs/PLDs into one FPGA, an even greater reduction in board-level power dissipation can be achieved. The power due to standby current is typically a small component of the overall power. Standby power is calculated below for commercial, worst case conditions. ICC VCC Power 2 mA 5.25V 10.5 mW The static power dissipated by TTL loads depends on the number of outputs driving high or low and the DC load current. Again, this value is typically small. For instance, a 32-bit bus sinking 4 mA at 0.33 V will generate 42 mW with all outputs driving low, and 140 mW with all outputs driving high. The actual dissipation will average somewhere between as I/Os switch states with time. Ac ti v e P o wer Com p o nent Power dissipation in CMOS devices is usually dominated by the active (dynamic) power dissipation. This component is frequency dependent, a function of the logic and the external I/O. Active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitance due to PC board traces Package Type Pin Count θjc θja Still Air θja 300 ft/min Units Ceramic Pin Grid Array 100 132 176 5 5 8 35 30 23 17 15 12 °C/W °C/W °C/W Ceramic Quad Flat Pack 172 8 25 15 °C/W Plastic Quad Flat Pack1 100 144 160 13 15 15 48 40 38 40 32 30 °C/W °C/W °C/W Plastic Leaded Chip Carrier2 84 12 37 28 °C/W Very Thin Quad Flat Pack3 100 12 43 35 °C/W Thin Quad Flat Pack4 176 15 32 25 °C/W Notes:(Maximum Power in Still Air) 1. Maximum Power Dissipation for PQFP packages are 1.9 Watts (100-pin), 2.3 Watts (144-pin), and 2.4 Watts (160-pin). 2. Maximum Power Dissipation for PLCC packages is 2.7 Watts. 3. Maximum Power Dissipation for VQFP packages is 2.3 Watts. 4. Maximum Power Dissipation for TQFP packages is 3.1 Watts. Max. junction temp. (°C) – Max. commercial temp. θja (°C/W) ----------------------------------------------------------------------------------------------------------------------------- 150°C – 70°C 33°C/W --------------------------------- 2.4 W == |
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