June 2006

i

© 2006 Actel Corporation

eX Automotive Family FPGAs

Specifications

•

3,000 to 12,000 Available System Gates

•

Maximum 512 Flip-Flops (Using CC Macros)

•

0.22

µm CMOS Process Technology

•

Up to 132 User-Programmable I/O Pins

Features

•

250 MHz Internal Performance, Low-Power Antifuse

FPGA

•

Advanced Small-Footprint Packages

•

Pin-to-Pin Compatibility with eX Commercial- and

Industrial-Grade Devices

•

Hot-Swap Compliant I/Os

•

Single-Chip Solution

•Nonvolatile

•

Live on Power-Up

•

No Power-Up/Down Sequence Required for Supply

Voltages

•

Configurable Weak Resistor Pull-Up or Pull-Down

for Tristated Outputs during Power-Up

•

Individual Output Slew-Rate Control

•

2.5 V and 3.3 V I/Os

•

Software Design Support with Actel Designer and

Tools

•

Up to 100% Resource Utilization with 100% Pin

Locking

•

Deterministic Timing

•

Unique In-System Diagnostic and Verification

Capability with Silicon Explorer II

•

Boundary Scan Testing in Compliance with IEEE

Standard 1149.1 (JTAG)

•

FuseLock™

Secure

Programming

Technology

Prevents Reverse Engineering and Design Theft

Product Profile

™

e

u

Device

eX64

eX128

eX256

Capacity

System Gates

Typical Gates

3,000

2,000

6,000

4,000

12,000

8,000

Register Cells

Dedicated Flip-Flops

Maximum Flip-Flops

64

128

128

256

256

512

Combinatorial Cells

128

256

512

Maximum User I/Os

84

100

132

Global Clocks

Hardwired

Routed

1

2

1

2

1

2

Speed Grades*

Std.

Std.

Std.

Temperature Grades*

AA

A

Package (by pin count)

TQFP

CSP

64, 100

49, 128

64, 100

49, 128

100

128, 180

Note: * The eX family is also offered in commercial and industrial temperature grades with –F, –P, and Std. speed grades. Refer to the eX

Family FPGAs datasheet for more details.

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