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A54SX32A-CQ208B Datasheet(PDF) 1 Page - Actel Corporation |
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A54SX32A-CQ208B Datasheet(HTML) 1 Page - Actel Corporation |
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1 / 50 page  Nove mber 2006 i © 2006 Actel Corporation See the Actel website for the latest version of the datasheet. HiRel SX-A Family FPGAs Features and Benefits Leading Edge Performance • 215 MHz System Performance (Military Temperature) • 5.3 ns Clock-to-Out (Pin-to-Pin) (Military Temperature) • 240 MHz Internal Performance (Military Temperature) Specifications • 48,000 to 108,000 Available System Gates • Up to 228 User-Programmable I/O Pins • Up to 2,012 Dedicated Flip-Flops • 0.25/0.22 µ CMOS Process Technology Features • Hot-Swap Compliant I/Os • Power-Up/Down Friendly (no sequencing required for supply voltages) • Class B Level Devices • Three Standard Hermetic Package Options Product Profile • Actel Secure Programming Technology with FuseLock™ Prevents Reverse Engineering and Design Theft • Cold-Sparing Capability • Individual Output Slew Rate Control • QML Certified Devices • 100% Military Temperature Tested (–55°C to +125°C) • 33 MHz PCI Compliant • CPLD and FPGA Integration • Single-Chip Solution • Configurable I/O Support for 3.3 V/5 V PCI, LVTTL, and TTL • Configurable Weak Resistor Pull-Up or Pull-Down for Tristated Outputs during Power-Up • Up to 100% Resource Utilization and 100% Pin Locking • 2.5 V, 3.3 V, and 5 V Mixed Voltage Operation with 5 V Input Tolerance and 5 V Drive Strength • Very Low Power Consumption • Deterministic, User-Controllable Timing • Unique In-System Diagnostic and Verification Capability with Silicon Explorer II • Boundary-Scan Testing in Compliance with IEEE 1149.1 (JTAG) Device A54SX32A A54SX72A Capacity Typical Gates System Gates 32,000 48,000 72,000 108,000 Logic Modules Combinatorial Cells 2,880 1,800 6,036 4,024 Register Cells Dedicated Flip-Flops Maximum Flip-Flops 1,080 1,980 2,012 4,024 Maximum User I/Os 228 213 Global Clocks 33 Quadrant Clocks 04 Boundary-Scan Testing Yes Yes 3.3 V / 5 V PCI Yes Yes Clock-to-Out 5.3 ns 6.7 ns Input Set-Up (External) 0 ns 0 ns Speed Grades Std, –1 Std, –1 Package (by Pin Count) CQFP 84, 208, 256 208, 256 v2.0 |
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