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1553BBC-UR Datasheet(PDF) 2 Page - Actel Corporation |
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1553BBC-UR Datasheet(HTML) 2 Page - Actel Corporation |
2 / 30 page Core1553BBC MIL-STD-1553B Bus Controller 2 v4.0 General Description The Core1553BBC provides a complete, MIL-STD-1553B Bus Controller (BC). A typical system implementation using the Core1553BBC is shown in Figure 1. Core1553BBC reads message descriptor blocks from the memory and generates messages that are transmitted on the 1553B bus. Data words are read from the memory and transmitted on the 1553B bus. Data received is written to the memory. The core can be configured directly to connect to synchronous or asynchronous memory devices. The core consists of five main blocks: the 1553B encoder, the 1553B decoder, a protocol controller block, a CPU interface, and a backend interface (Figure 2). Figure 1 • Typical Core1553BBC System Figure 2 • Core1553BBC BC Block Diagram Actel FPGA BUSAINEN BUSAINP BUSAINN BUSAOUTINH BUSAOUTP BUSAOUTN BUSBINEN BUSBINP BUSBIN BUSAOUTINH BUSBOUTP BUSBOUTN RCVSTBA RXDAIN RXDAIN TXINHA TXDAIN TXDAIN Transceiver (Not Included) RCVSTBA RXDBIN RXDBIN TXINHA TXDBIN TXDBIN Memory CPU Glue Logic Core1553BBC Core1553BBC Encoder Decoder Backend Interface Protocol Controller BusA BusB Memory 64K*16 CPU Interface and Registers |
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Similar Description - 1553BBC-UR |
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