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A1225XL-1PQC Datasheet(PDF) 11 Page - Actel Corporation |
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A1225XL-1PQC Datasheet(HTML) 11 Page - Actel Corporation |
11 / 84 page Table 1 • IEEE 1149.1 BST Signals Signal Name Function TDI Test Data In Serial data input for BST instructions and data. Data is shifted in on the rising edge of TCK. TDO Test Data Out Serial data output for BST instructions and test data. TMS Test Mode Select Serial data input for BST mode. Data is shifted in on the rising edge of TCK. TCK Test Clock Clock signal to shift the BST data into the device. Discontinued – v3.0 11 Integrato r Se ries F P G A s: 1200 XL and 320 0DX Fam ilies JTAG All 3200DX devices are IEEE 1149.1 (JTAG) compliant. 3200DX devices offer superior diagnostic and testing capabilities by providing JTAG and probing capabilites. These functions are controlled through the special JTAG pins in conjunction with the program fuse. JTAG fuse programmed: • TCK must be terminated—logical high or low doesn’t matter (to avoid floating input) • TDI, TMS may float or at logical high (internal pull-up is present) • TDO may float or connect to TDI of another device (it’s an output) JTAG fuse not programmed: • TCK, TDI, TDO, TMS are user I/O. If not used, they will be configured as tristated output. BST Instructions Boundary scan testing within the 3200DX devices is controlled by a Test Access Port (TAP) state machine. The TAP controller drives the three-bit instruction register, a bypass register, and the boundary scan data registers within the device. The TAP controller uses the TMS signal to control the testing of the device. The BST mode is determined by the bitstream entered on the TMS pin. Table 2 describes the test instructions supported by the 3200DX devices. Reset The TMS pin is equipped with an internal pull-up resistor. This allows the TAP controller to remain in or return to the Test-Logic-Reset state when there is no input or when a logical 1 is on the TMS pin. To reset the controller, TMS must be HIGH for at least five TCK cycles. Table 2 • BST Instructions Test Mode Code Description EXTEST 000 Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. SAMPLE/ PRELOAD 001 Allows a snapshot of the signals at the device pins to be captured and examined during device operation. JPROBE 011 A private instruction allowing the user to connect Actel’s Micro Probe registers to the test chain. USER INSTRUCTION 100 Allows the user to build application-specific instructions such as RAM READ and RAM WRITE. HIGH Z 101 Refer to the IEEE Standard 1149.1 specification. CLAMP 110 Refer to the IEEE Standard 1149.1 specification. BYPASS 111 Enables the bypass register between the TDI and TDO pins. The test data passes through the selected device to adjacent devices in the test chain. When a device is operating in BST mode, four I/O pins are used for the TDI, TDO, TMS, and TCLK signals. An active reset (nTRST) pin is not supported; however, the 3200DX contains power-on circuitry which automatically resets the BST circuitry upon power-up. The following table summarizes the functions of the BST signals. JTAG BST Instructions JTAG BST testing within the 3200DX devices is controlled by a Test Access Port (TAP) state machine. The TAP controller drives the three-bit instruction register, a bypass register, and the boundary scan data registers within the device. The TAP controller uses the TMS signal to control the JTAG testing of the device. The JTAG test mode is determined by the bitstream entered on the TMS pin. The table in the next column describes the JTAG instructions supported by the 3200DX. Design Tool Support ActionProbe If a device has been successfully programmed and the security fuse has not been programmed, any internal logic or I/O module output can be observed in real time using the ActionProbe circuitry, the PRA and/or PRB pins, and Actel’s Silicon Explorer diagnostic and debug tool kit. |
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