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LT6556IUF Datasheet(PDF) 10 Page - Linear Technology |
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LT6556IUF Datasheet(HTML) 10 Page - Linear Technology |
10 / 16 page LT6556 10 6556f APPLICATIO S I FOR ATIO In order to counteract any peaking in the frequency re- sponse from driving a capacitive load, a series resistance can be inserted in the line at the output of the part to flat- ten the response. Figure 4 shows the frequency response with the same 4cm trace from Figure 3, now with a 10Ω series resistor inserted near the output pin of the ampli- fier. Note that using a 10Ω series resistor with a 1k load only decreases the output amplitude by 0.1dB or 1% and has a minimal effect on the bandwidth of the system. See the graph labeled “Maximum Capacitive Load vs Output Series Resistor” in the Typical Performance Characteristics section for more information. FREQUENCY (MHz) 0.1 6 4 2 0 –2 –4 –6 1 10 100 1000 6556 F04 4cm TRACE 4cm TRACE RS, OUT = 10Ω VS = ±5V VOUT = 200mVP-P RL = 1k TA = 25°C Figure 4. Response vs Series Output Resistance While the AGND pins on the LT6556 are not connected to the amplifier circuitry, tying them to ground or another “quiet” node significantly increases channel isolation and is always recommended. The AGND pins do have ESD protection and therefore should not be connected to potentials outside the power supply range. Low ESL/ESR bypass capacitors should be placed as close to the positive and negative supply pins as possible. One 4700pF ceramic capacitor is recommended for both V+ and V–supply busses. Additional 470pF ceramic capacitors with minimal trace length on each supply pin will further improve AC and transient response as well as channel isolation. For high current drive and large-signal transient applications, additional 1µF to 10µF tantalums should be added on each supply. The smallest value capacitors should be placed closest to the package. To maintain the LT6556’s channel isolation, it is beneficial to shield parallel input and parallel output traces using a ground plane or power supply traces. Vias between top- side and backside metal may be required to maintain a low inductance ground near the part where numerous traces converge. See Figures 7 and 8 for photos of an optimized layout. Single Supply Operation Figure 5 illustrates how to use the LT6556 with a single supply ranging from 4.5V to 12V. Since the output range is comparable to the input range, the DC bias point at the input can be set anywhere between the supplies that will prevent the AC-coupled signal from running into the output range limits. As shown, the DC input level is mid-supply. The only additional power dissipation in the single supply configuration is through the resistor bias string at the input and through any load resistance at the output. In many cases, the output can be used to directly drive other single supply devices without additional coupling and without any resistive load. 1/3 LT6556 5k 5k AGND IN VIN 22μF OUT V+ V– 4.5V TO 12V 6556 F05 Figure 5. Single Supply Configuration, One Channel Shown Input Expansion In applications with more than two inputs per channel, multiple LT6556s can be connected directly together at the outputs. Logic circuitry can be used to drive the ⎯E⎯N pins of each LT6556 to ensure that only one set of channels is buffered at a time. See Figure 9 for a schematic. Since the output impedance of a disabled LT6556 is high, adding additional channels will not resistively load an |
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