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LT6559 Datasheet(PDF) 9 Page - Linear Technology |
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LT6559 Datasheet(HTML) 9 Page - Linear Technology |
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9 / 16 page  LT6559 9 6559f APPLICATIONS INFORMATION internal capacitance. At a gain of 2 with 301Ω feedback and gain resistors and ±5V supplies, the output slew rate is typically 800V/µs. Larger feedback resistors will reduce the slew rate as will lower supply voltages. Enable/Disable Each amplifier of the LT6559 has a unique high imped- ance, zero supply current mode which is controlled by its own ⎯E⎯N pin. These amplifiers are designed to operate with CMOS logic; the amplifiers draw 0.1µA of current when these pins are high or floated. To activate each amplifier, its ⎯E⎯N pin is normally pulled to a logic low. However, sup- ply current will vary as the voltage between the V+ supply and ⎯E⎯N is varied. As seen in Figure 1, +IS does vary with (V+ – V⎯E⎯N), particularly when the voltage difference is less than 3V. For normal operation, it is important to keep the ⎯E⎯N pin at least 3V below the V+ supply. If a V+ of less than 3V is used, for the amplifier to remain enabled at all times the ⎯E⎯N pin should be tied to the V– supply. The enable pin current is approximately 30µA when activated. If using CMOS open-drain logic, an external 1k pull-up resistor is recommended to ensure that the LT6559 remains disabled regardless of any CMOS drain-leakage currents. Differential Input Signal Swing To avoid any breakdown condition on the input transis- tors, the differential input swing must be limited to ±5V. In normal operation, the differential voltage between the input pins is small, so the ±5V limit is not an issue. In the disabled mode however, the differential swing can be the same as the input swing, and there is a risk of device breakdown if the input voltage range has not been properly considered. V + – VEN (V) 0 0 0.5 1.5 2.0 2.5 5.0 3.5 2 4 5 6559 F01 1.0 4.0 4.5 3.0 1 3 6 7 TA = 25°C V + = 5V V – = – 5V V – = 0V Figure 1. +IS vs (V + – V⎯E⎯N) The enable/disable times are very fast when driven from standard 5V CMOS logic. Each amplifier enables in about 30ns (50% point to 50% point) while operating on ±5V supplies (Figure 2). Likewise, the disable time is approxi- mately 40ns (50% point to 50% point) (Figure 3). Figure 2. Amplifier Enable Time, AV = 2 Figure 3. Amplifier Disable Time, AV = 2 2V 0V 5V 0V OUTPUT 6559 F02 VS = ±5V VIN = 1V RF = 301Ω RG = 301Ω RL = 100Ω EN 6559 F03 VS = ±5V VIN = 1V RF = 301Ω RG = 301Ω RL = 100Ω 2V 0V 5V 0V OUTPUT EN |
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