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M1AFS600-2FGG256ES Datasheet(PDF) 1 Page - Actel Corporation |
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M1AFS600-2FGG256ES Datasheet(HTML) 1 Page - Actel Corporation |
1 / 318 page October 2008 I © 2008 Actel Corporation Actel Fusion Mixed-Signal FPGAs Family with Optional ARM® Support Features and Benefits High-Performance Reprogrammable Flash Technology • Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process • Nonvolatile, Retains Program when Powered Off • Live at Power-Up (LAPU) Single-Chip Solution • 350 MHz System Performance Embedded Flash Memory • User Flash Memory – 2 Mbits to 8 Mbits – Configurable 8-, 16-, or 32-Bit Datapath – 10 ns Access in Read-Ahead Mode • 1 kbit of Additional FlashROM Integrated A/D Converter (ADC) and Analog I/O • Up to 12-Bit Resolution and up to 600 ksps • Internal 2.56 V or External Reference Voltage • ADC: Up to 30 Scalable Analog Input Channels • High-Voltage Input Tolerance: –10.5 V to +12 V • Current Monitor and Temperature Monitor Blocks • Up to 10 MOSFET Gate Driver Outputs – P- and N-Channel Power MOSFET Support – Programmable 1, 3, 10, 30 µA and 20 mA Drive Strengths • ADC Accuracy is Better than 1% On-Chip Clocking Support • Internal 100 MHz RC Oscillator (accurate to 1%) • Crystal Oscillator Support (32 kHz to 20 MHz) • Programmable Real-Time Counter (RTC) • 6 Clock Conditioning Circuits (CCCs) with 1 or 2 Integrated PLLs – Phase Shift, Multiply/Divide, and Delay Capabilities – Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz Low Power Consumption • Single 3.3 V Power Supply with On-Chip 1.5 V Regulator • Sleep and Standby Low Power Modes In-System Programming (ISP) and Security • Secure ISP with 128-Bit AES via JTAG •FlashLock® to Secure FPGA Contents Advanced Digital I/O • 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation • Bank-Selectable I/O Voltages – Up to 5 Banks per Chip • Single-Ended I/O Standards: LVTTL, LVCMOS 3.3V/2.5 V/1.8V/1.5 V, 3.3VPCI / 3.3VPCI-X, and LVCMOS 2.5 V / 5.0 V Input • Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS – Built-In I/O Registers – 700 Mbps DDR Operation • Hot-Swappable I/Os • Programmable Output Slew Rate, Drive Strength, and Weak Pull-Up/Down Resistor • Pin-Compatible Packages across the Fusion Family SRAMs and FIFOs • Variable-Aspect-Ratio 4,608-Bit SRAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations available) • True Dual-Port SRAM (except ×18) • Programmable Embedded FIFO Control Logic Soft ARM7™ Core Support in M7 and M1 Fusion Devices • ARM Cortex™-M1 (without debug), CoreMP7Sd (with debug) and CoreMP7S (without debug) ® Fusion Family Fusion Devices AFS090 AFS250 AFS600 AFS1500 ARM-Enabled Fusion Devices CoreMP7 1 M7AFS600 Cortex-M1 2 M1AFS250 M1AFS600 M1AFS1500 General Information System Gates 90,000 250,000 600,000 1,500,000 Tiles (D-flip-flops) 2,304 6,144 13,824 38,400 Secure (AES) ISP Yes Yes Yes Yes PLLs 1 1 2 2 Globals 18181818 Memory Flash Memory Blocks (2 Mbits) 1 1 2 4 Total Flash Memory Bits 2 M 2 M 4 M 8 M FlashROM Bits 1 k 1 k 1 k 1 k RAM Blocks (4,608 bits) 6 8 24 60 RAM kbits 27 36 108 270 Analog and I/Os Analog Quads 5 6 10 10 Analog Input Channels 15 18 30 30 Gate Driver Outputs 5 6 10 10 I/O Banks (+ JTAG) 4 4 5 5 Maximum Digital I/Os 75 114 172 252 Analog I/Os 20 24 40 40 Notes: 1. Refer to the CoreMP7 datasheet for more information. 2. Refer to the Cortex-M1 product brief for more information. Preliminary v1.7 |
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