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AX250-CGG896PP Datasheet(PDF) 7 Page - Actel Corporation |
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AX250-CGG896PP Datasheet(HTML) 7 Page - Actel Corporation |
7 / 226 page Axcelerator Family FPGAs v2.7 1-1 General Description Axcelerator offers high performance at densities of up to two million equivalent system gates. Based upon the Actel AX architecture, Axcelerator has several system- level features such as embedded SRAM (with complete FIFO control logic), PLLs, segmentable clocks, chip-wide highway routing, and carry logic. Device Architecture Actel's AX architecture, derived from the highly- successful SX-A sea-of-modules architecture, has been designed for high performance and total logic module utilization (Figure 1-1). Unlike in traditional FPGAs, the entire floor of the Axcelerator device is covered with a grid of logic modules, with virtually no chip area lost to interconnect elements or routing. Programmable Interconnect Element The Axcelerator family uses a patented metal-to-metal antifuse programmable interconnect element that resides between the upper two layers of metal (Figure 1-2 on page 1-2). This completely eliminates the channels of routing and interconnect resources between logic modules (as implemented on traditional FPGAs) and enables the efficient sea-of-modules architecture. The antifuses are normally open circuit and, when programmed, form a permanent, passive, low- impedance connection, leading to the fastest signal propagation in the industry. In addition, the extremely small size of these interconnect elements gives the Axcelerator family abundant routing resources. The very nature of Actel's nonvolatile antifuse technology provides excellent protection against design pirating and cloning (FuseLock technology). Cloning is impossible (even if the security fuse is left unprogrammed) as no bitstream or programming file is ever downloaded or stored in the device. Reverse engineering is virtually impossible due to the difficulty of trying to distinguish between programmed and unprogrammed antifuses and also due to the programming methodology of antifuse devices (see "Security" on page 2-90). Figure 1-1 • Sea-of-Modules Comparison Switch Matrix Routing Logic Block Logic Modules Sea-of-Modules Architecture Traditional FPGA Architecture |
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