Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

A1280XL-FPQC Datasheet(PDF) 11 Page - Actel Corporation

Part # A1280XL-FPQC
Description  Integrator Series FPGAs: 1200XL and 3200DX Families
Download  84 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ACTEL [Actel Corporation]
Direct Link  http://www.actel.com
Logo ACTEL - Actel Corporation

A1280XL-FPQC Datasheet(HTML) 11 Page - Actel Corporation

Back Button A1280XL-FPQC Datasheet HTML 7Page - Actel Corporation A1280XL-FPQC Datasheet HTML 8Page - Actel Corporation A1280XL-FPQC Datasheet HTML 9Page - Actel Corporation A1280XL-FPQC Datasheet HTML 10Page - Actel Corporation A1280XL-FPQC Datasheet HTML 11Page - Actel Corporation A1280XL-FPQC Datasheet HTML 12Page - Actel Corporation A1280XL-FPQC Datasheet HTML 13Page - Actel Corporation A1280XL-FPQC Datasheet HTML 14Page - Actel Corporation A1280XL-FPQC Datasheet HTML 15Page - Actel Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 11 / 84 page
background image
Table 1 • IEEE 1149.1 BST Signals
Signal
Name
Function
TDI
Test Data In
Serial data input for BST instructions and
data. Data is shifted in on the rising edge
of TCK.
TDO
Test Data Out
Serial data output for BST instructions
and test data.
TMS
Test Mode Select
Serial data input for BST mode. Data is
shifted in on the rising edge of TCK.
TCK
Test Clock
Clock signal to shift the BST data into
the device.
Discontinued – v3.0
11
Integrato r Se ries F P G A s: 1200 XL and 320 0DX Fam ilies
JTAG
All 3200DX devices are IEEE 1149.1 (JTAG) compliant.
3200DX devices offer superior diagnostic and testing
capabilities by providing JTAG and probing capabilites.
These functions are controlled through the special JTAG
pins in conjunction with the program fuse.
JTAG fuse programmed:
• TCK must be terminated—logical high or low doesn’t
matter (to avoid floating input)
• TDI, TMS may float or at logical high (internal pull-up is
present)
• TDO may float or connect to TDI of another device (it’s an
output)
JTAG fuse not programmed:
• TCK, TDI, TDO, TMS are user I/O. If not used, they will be
configured as tristated output.
BST Instructions
Boundary scan testing within the 3200DX devices is
controlled by a Test Access Port (TAP) state machine. The
TAP controller drives the three-bit instruction register, a
bypass register, and the boundary scan data registers within
the device. The TAP controller uses the TMS signal to
control the testing of the device. The BST mode is
determined by the bitstream entered on the TMS pin.
Table 2 describes the test instructions supported by the
3200DX devices.
Reset
The TMS pin is equipped with an internal pull-up resistor.
This allows the TAP controller to remain in or return to the
Test-Logic-Reset state when there is no input or when a
logical 1 is on the TMS pin. To reset the controller, TMS
must be HIGH for at least five TCK cycles.
Table 2 • BST Instructions
Test Mode
Code
Description
EXTEST
000
Allows the external circuitry and
board-level interconnections to be tested
by forcing a test pattern at the output pins
and capturing test results at the input
pins.
SAMPLE/
PRELOAD
001
Allows a snapshot of the signals at the
device pins to be captured and examined
during device operation.
JPROBE
011
A private instruction allowing the user to
connect Actel’s Micro Probe registers to
the test chain.
USER
INSTRUCTION
100
Allows the user to build
application-specific instructions such as
RAM READ and RAM WRITE.
HIGH Z
101
Refer to the IEEE Standard 1149.1
specification.
CLAMP
110
Refer to the IEEE Standard 1149.1
specification.
BYPASS
111
Enables the bypass register between the
TDI and TDO pins. The test data passes
through the selected device to adjacent
devices in the test chain.
When a device is operating in BST mode, four I/O pins are
used for the TDI, TDO, TMS, and TCLK signals. An active
reset (nTRST) pin is not supported; however, the 3200DX
contains power-on circuitry which automatically resets the
BST
circuitry
upon
power-up.
The
following
table
summarizes the functions of the BST signals.
JTAG BST Instructions
JTAG BST testing within the 3200DX devices is controlled
by a Test Access Port (TAP) state machine. The TAP
controller drives the three-bit instruction register, a bypass
register, and the boundary scan data registers within the
device. The TAP controller uses the TMS signal to control
the JTAG testing of the device. The JTAG test mode is
determined by the bitstream entered on the TMS pin. The
table in the next column describes the JTAG instructions
supported by the 3200DX.
Design Tool Support ActionProbe
If a device has been successfully programmed and the
security fuse has not been programmed, any internal logic
or I/O module output can be observed in real time using the
ActionProbe circuitry, the PRA and/or PRB pins, and Actel’s
Silicon Explorer diagnostic and debug tool kit.


Similar Part No. - A1280XL-FPQC

ManufacturerPart #DatasheetDescription
logo
Actel Corporation
A1280 ACTEL-A1280 Datasheet
1Mb / 98P
   Highly Predictable Performance with 100% Automatic Placement and Routing
logo
Microsemi Corporation
A1280A MICROSEMI-A1280A Datasheet
2Mb / 54P
   ACT 2 Family FPGAs
A1280A-1CQ160B MICROSEMI-A1280A-1CQ160B Datasheet
2Mb / 54P
   ACT 2 Family FPGAs
A1280A-1CQ160C MICROSEMI-A1280A-1CQ160C Datasheet
2Mb / 54P
   ACT 2 Family FPGAs
A1280A-1CQ160I MICROSEMI-A1280A-1CQ160I Datasheet
2Mb / 54P
   ACT 2 Family FPGAs
More results

Similar Description - A1280XL-FPQC

ManufacturerPart #DatasheetDescription
logo
Fuji Electric
EDS10-12E FUJI-EDS10-12E Datasheet
63Kb / 4P
   FC SERIES INTEGRATOR
EDS10-13D FUJI-EDS10-13D Datasheet
71Kb / 2P
   FC SERIES PULSE INTEGRATOR
EDS10-17E FUJI-EDS10-17E Datasheet
131Kb / 8P
   FC SERIES ELECTRONIC INTEGRATOR
logo
List of Unclassifed Man...
A40MX02 ETC1-A40MX02 Datasheet
854Kb / 123P
   40MX and 42MX FPGA Families
logo
Microsemi Corporation
A42MX24-2PQ160 MICROSEMI-A42MX24-2PQ160 Datasheet
7Mb / 143P
   40MX and 42MX FPGA Families
A40MX04-PL44I MICROSEMI-A40MX04-PL44I Datasheet
7Mb / 143P
   40MX and 42MX FPGA Families
A40MX02-PL44 MICROSEMI-A40MX02-PL44 Datasheet
7Mb / 142P
   40MX and 42MX FPGA Families
A40MX04-PLG44 MICROSEMI-A40MX04-PLG44 Datasheet
7Mb / 142P
   40MX and 42MX FPGA Families
logo
Actel Corporation
A42MX16-1PQ100ES ACTEL-A42MX16-1PQ100ES Datasheet
908Kb / 123P
   40MX and 42MX FPGA Families
logo
Microsemi Corporation
A42MX24-PQ208I MICROSEMI-A42MX24-PQ208I Datasheet
7Mb / 142P
   40MX and 42MX FPGA Families
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.NET
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com