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RT54SX72S Datasheet(PDF) 8 Page - Actel Corporation

Part # RT54SX72S
Description  RTSX-S RadTolerant FPGAs
Download  84 Pages
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Manufacturer  ACTEL [Actel Corporation]
Direct Link  http://www.actel.com
Logo ACTEL - Actel Corporation

RT54SX72S Datasheet(HTML) 8 Page - Actel Corporation

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RTSX-S RadTolerant FPGAs
1- 2
v2.2
These antifuse interconnects reside between the top two
layers of metal and thereby enable the sea-of-modules
architecture in an FPGA.
The extremely small size of these interconnect elements
gives the RTSX-S family abundant routing resources and
provides excellent protection against design theft.
Reverse engineering is virtually impossible because it is
extremely difficult to distinguish between programmed
and unprogrammed antifuses. Additionally, since RTSX-S
is a nonvolatile, single-chip solution, there is no
configuration bitstream to intercept.
The RTSX-S interconnect (i.e., the antifuses and metal
tracks) also has lower capacitance and resistance than
that of any other device of similar capacity, leading to
the fastest signal propagation in the industry for the
radiation tolerance offered.
I/O Structure
The RTSX-S family features a flexible I/O structure that
supports 3.3V LVTTL, 5V TTL, 5V CMOS, and 3.3V and 5V
PCI. All I/O standards are hot-swap compliant, cold-
sparing capable, and 5V tolerant (except for 3.3V PCI).
In addition, each I/O on an RTSX-S device can be
configured as an input, an output, a tristate output, or a
bidirectional pin. Mixed I/O standards are allowed and
can be set on a pin-by-pin basis. High or low slew rate
can be set on individual output buffers (except for PCI,
which defaults to high slew), as well as the power-up
configuration (either pull-up or pull-down).
Even without the inclusion of dedicated I/O registers,
these I/Os, in combination with array registers, can
achieve clock-to-output-pad timing as fast as 9.5 ns. In
most FPGAs, I/O cells that have embedded latches and
flip-flops require instantiation in HDL code; this is a
design complication not encountered in RTSX-S FPGAs.
Fast pin-to-pin timing ensures that the device will have
little trouble interfacing with any other device in the
system, which in turn, enables parallel design of system
components and reduces overall design time.
Logic Modules
Actel’s RTSX-S family provides two types of logic modules
to the designer (Figure 1-2 on page 1-3): the register cell
(R-cell) and the combinatorial cell (C-cell).
The C-cell implements a range of combinatorial functions
with up to 5 inputs. Inclusion of the DB input and its
associated inverter function dramatically increases the
number
of
combinatorial
functions
that
can
be
implemented in a single module from 800 options (as in
previous architectures) to more than 4,000 in the RTSX-S
architecture. An example of the improved flexibility
enabled by the inversion capability is the ability to
integrate a three-input exclusive-OR function into a
single C-cell. This facilitates the construction of nine-bit
parity-tree functions. At the same time, the C-cell
structure is extremely synthesis-friendly, simplifying the
overall design and reducing synthesis time.
The R-cell contains a flip-flop featuring asynchronous
clear, asynchronous preset, and clock enable (using the
S0 and S1 lines) control signals. The R-cell registers
feature programmable clock polarity, selectable on a
register-by-register
basis.
This
provides
additional
flexibility during mapping of synthesized functions into
the RTSX-S FPGA. The clock source for the R-cell can be
chosen from the hardwired clock, the routed clocks, or
the internal logic.
While each SEU-hardened R-cell appears as a single D-
type flip-flop to the user, each is implemented employing
triple redundancy to achieve a LET threshold of greater
than 40 MeV-cm2/mg. Each TMR R-cell consists of three
master-slave latch pairs, each with asynchronous, self-
correcting feedback paths. The output of each latch on
the master or slave side is voted with the outputs of the
other two latches on that side. If one of the three latches
is struck by an ion and starts to change state, the voting
with the other two latches prevents the change from
feeding back and permanently latching. Care was taken
in the layout to ensure that a single ion strike could not
affect more than one latch (see "R-Cell" section on
page 2-23 for more details).
Actel has arranged all C-cell and R-cell logic modules into
horizontal banks called Clusters. There are two types of
clusters: Type 1 contains two C-cells and one R-cell, while
Type 2 contains one C-cell and two R-cells.
To increase design efficiency and device performance,
Actel
has
further
organized
these
modules
into
SuperClusters. SuperCluster 1 is a two-wide grouping of
Type 1 clusters. SuperCluster 2 is a two-wide group
containing one Type 1 cluster and one Type 2 cluster.
RTSX-S devices feature more SuperCluster 1 modules
than SuperCluster 2 modules because designers typically
require significantly more combinatorial logic than flip-
flops (Figure 1-2 on page 1-3).
Routing
R-cells and C-cells within Clusters and SuperClusters can
be connected through the use of two innovative local
routing resources called FastConnect and DirectConnect,
which
enable
extremely
fast
and
predictable
interconnection
of
modules
within
Clusters
and
SuperClusters. This routing architecture also dramatically
reduces the number of antifuses required to complete a
circuit, ensuring the highest possible performance
(Figure 1-3 on page 1-4 and Figure 1-4 on page 1-4).


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