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RTSX32SU Datasheet(PDF) 9 Page - Actel Corporation

Part # RTSX32SU
Description  RTSX-SU RadTolerant FPGAs (UMC)
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Manufacturer  ACTEL [Actel Corporation]
Direct Link  http://www.actel.com
Logo ACTEL - Actel Corporation

RTSX32SU Datasheet(HTML) 9 Page - Actel Corporation

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RTSX-SU RadTolerant FPGAs (UMC)
v2.2
1-3
Routing
R-cells and C-cells within Clusters and SuperClusters can
be connected through the use of two innovative local
routing resources called FastConnect and DirectConnect,
which
enable
extremely
fast
and
predictable
interconnection
of
modules
within
Clusters
and
SuperClusters. This routing architecture also dramatically
reduces the number of antifuses required to complete a
circuit, ensuring the highest possible performance
(Figure 1-3 and Figure 1-4 on page 1-4).
DirectConnect is a horizontal routing resource that
provides connections from a C-cell to its neighboring R-cell
in a given SuperCluster. DirectConnect uses a hardwired
signal path requiring no programmable interconnection to
achieve its fast signal propagation time of less than 0.1 ns.
FastConnect enables horizontal routing between any
two logic modules within a given SuperCluster and
vertical routing with the SuperCluster immediately
below it. Only one programmable connection is used in a
FastConnect path, delivering a maximum interconnect
propagation delay of 0.4 ns.
In addition to DirectConnect and FastConnect, the
architecture makes use of two globally-oriented routing
resources known as segmented routing and high-drive
routing. Actel’s segmented routing structure provides a
variety of track lengths for extremely fast routing
between SuperClusters. The exact combination of track
lengths and antifuses within each path is chosen by the
100-percent-automatic
place-and-route
software
to
minimize signal propagation delays.
Figure 1-2 • R-Cell, C-Cell and Cluster Organization
Type 1 SuperCluster
Type 2 SuperCluster
Cluster 1
Cluster 1
Cluster 2
Cluster 1
R-Cell
C-Cell
D0
D1
D2
D3
DB
A0 B0
A1 B1
Sa
Sb
Y
Direct
Connect
Input
CLKA,
CLKB,
Internal Logic
HCLK
CKS
CKP
CLR
PRE
Y
DQ
Routed
Data Input
S0
S1


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