September 2008

i

© 2008 Actel Corporation

See the Actel website for the latest version of the datasheet.

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RTAX-DSP Radiation-Tolerant FPGAs

Radiation Performance

•

SEU-Hardened Registers Eliminate the Need for Triple-

Module Redundancy (TMR)

–

Geosynchronous Orbit

•

Use of Error Detection and Correction (EDAC) IP

(included) with Integrated SRAM Scrubber

–

Single-Bit Correction, Double-Bit Detection

–

Variable-Rate Background Refreshing

•

Total Ionizing Dose Up to 300 krad (Si, Functional)

•

•

TM1019 Test Data Available

Embedded Multiply/Accumulate

Blocks

•

Up to 120 Multiply/Accumulate Blocks

•

Fully SEU- and SET-Hardened

•

125 MHz Performance throughout Military Temperature

Range

•

Flexible, Cascadable Accumulate Function

Processing Flows

•

B-Flow – MIL-STD-883B

•

E-Flow – Actel Extended Flow

•

EV-Flow – Class V Equivalent Flow Processing

Prototyping Options

•

RTAX-DSP PROTO Devices with Same Functional and

Timing Characteristics as Flight Unit in a Non-Hermetic

Package

Leading-Edge Performance

•

High-Performance Embedded FIFOs

•

350+ MHz System Performance

•

500+ MHz Internal Performance

•

700 Mbps LVDS Capable I/Os

Specifications

•

Up to 4 Million Equivalent System Gates or 500 k

Equivalent ASIC Gates

•

Up to 16,800 SEU-Hardened Flip-Flops

•

Up to 840 I/Os

•

Up to 540 kbits Embedded SRAM

•

Manufactured on Advanced 0.15

Process Technology, 7 Layers of Metal

Features

•

Single-Chip, Nonvolatile Solution

•

1.5 V Core Voltage for Low Power

•

Flexible, Multi-Standard I/Os:

–

1.5 V, 1.8 V, 2.5 V, 3.3 V Mixed Voltage Operation

–

Bank-Selectable I/Os – 8 Banks per Chip

–

Single-Ended I/O Standards: LVTTL, LVCMOS, 3.3 V PCI

–

JTAG Boundary Scan Testing (as per IEEE 1149.1)

–

Differential I/O Standards: LVPECL and LVDS

–

Voltage-Referenced

I/O

Standards:

GTL+,

HSTL

Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2

–

Hot-Swap Compliant with Cold-Sparing Support

(Except PCI)

•

Embedded Memory with Variable Aspect Ratio and

Organizations:

–

Independent, Width-Configurable Read and Write

Ports

–

Programmable Embedded FIFO Control Logic

–

ROM Emulation Capability

•

Deterministic, User-Controllable Timing

•

Unique In-System Diagnostic and Debug Capability

Table 1 •

RTAX-DSP Family Product Profile

Device

RTAX2000D

RTAX4000D

Capacity

Equivalent System Gates

ASIC Gates

2,000,000

250,000

4,000,000

500,000

Modules

Register (R-cells)

Combinatorial (C-cells)

Flip-Flops (maximum)

8,960

17,920

17,920

16,800

33,600

33,600

Embedded Multiply / Accumulate Blocks

DSP Mathblocks

64

120

Embedded RAM/FIFO (without EDAC)

Core RAM Blocks

Core RAM Bits (k = 1,024)

64

288 k

120

540 k

Clocks (segmentable)

Hardwired

Routed

4

4

4

4

I/Os

I/O Banks

User I/Os (maximum)

I/O Registers

8

684

2,052

8

840

2,520

Package

CCGA/LGA

1152

1272

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