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A54SX16-CG256 Datasheet(PDF) 11 Page - Actel Corporation |
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A54SX16-CG256 Datasheet(HTML) 11 Page - Actel Corporation |
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11 / 46 page  SX Family FPGAs RadTolerant and HiRel v2.1 1-7 Clock Resources Actel’s high-drive routing structure provides three clock networks. The first clock, called HCLK, is hardwired from the HCLK buffer to the clock select MUX in each R-cell. HCLK cannot be connected to combinational logic. This provides a fast propagation path for the clock signal, enabling the 8.9 ns clock-to-out (pad-to-pad) performance of the RTSX devices. The hardwired clock is tuned to provide clock skew is less than 0.5 ns worst case. The remaining two clocks (CLKA and CLKB) are global clocks that can be sourced from external pins or from internal logic signals within the RTSX device. CLKA and CLKB may be connected to sequential cells or to combinational logic. If CLKA or CLKB is sourced from internal logic signals, then the external clock pin cannot be used for any other input and must be tied low or high. Figure 1-8 describes the clock circuit used for the constant load HCLK. Figure 1-9 describes the CLKA and CLKB circuit used in all RTSX devices with the exception of the RT54SX72S device. Figure 1-7 • DirectConnect and FastConnect for Type 2 SuperClusters Type 2 SuperClusters FastConnect • One Antifuse DirectConnect • No Antifuses Routing Segments • Typically Two Antifuses • Max. Five antifuses Figure 1-8 • RTSX Constant Load Clock Pad Figure 1-9 • RTSX Clock Pads Constant Load HCLKBUF Clock Network Clock Network From Internal Logic CLKBUF CLKBUFI CLKINT CLKINTI |
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