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RTSX72SU-CC256B Datasheet(PDF) 8 Page - Actel Corporation

Part # RTSX72SU-CC256B
Description  RTSX-SU RadTolerant FPGAs (UMC)
Download  83 Pages
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Manufacturer  ACTEL [Actel Corporation]
Direct Link  http://www.actel.com
Logo ACTEL - Actel Corporation

RTSX72SU-CC256B Datasheet(HTML) 8 Page - Actel Corporation

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RTSX-SU RadTolerant FPGAs (UMC)
1- 2
v2.2
Logic Modules
Actel’s RTSX-SU family provides two types of logic
modules to the designer (Figure 1-2 on page 1-3): the
register cell (R-cell) and the combinatorial cell (C-cell).
The C-cell implements a range of combinatorial functions
with up to five inputs. Inclusion of the DB input and its
associated inverter function dramatically increases the
number
of
combinatorial
functions
that
can
be
implemented in a single module from 800 options (as in
previous architectures) to more than 4,000 in the RTSX-SU
architecture. An example of the improved flexibility
enabled by the inversion capability is the ability to
integrate a three-input exclusive-OR function into a single
C-cell. This facilitates the construction of nine-bit parity-
tree functions. At the same time, the C-cell structure is
extremely synthesis-friendly, simplifying the overall design
and reducing synthesis time.
The R-cell contains a flip-flop featuring asynchronous
clear, asynchronous preset, and clock enable (using the
S0 and S1 lines) control signals. The R-cell registers
feature programmable clock polarity, selectable on a
register-by-register
basis.
This
provides
additional
flexibility during mapping of synthesized functions into
the RTSX-SU FPGA. The clock source for the R-cell can be
chosen from the hardwired clock, the routed clocks, or
the internal logic.
While each SEU-hardened R-cell appears as a single D-type
flip-flop to the user, each is implemented employing triple
redundancy to achieve a LET threshold of greater than 40
MeV-cm2/mg. Each TMR R-cell consists of three master-
slave latch pairs, each with asynchronous, self-correcting
feedback paths. The output of each latch on the master or
slave side is voted with the outputs of the other two
latches on that side. If one of the three latches is struck by
an ion and starts to change state, the voting with the
other two latches prevents the change from feeding back
and permanently latching. Care was taken in the layout to
ensure that a single ion strike could not affect more than
one latch (see the "R-Cell" section on page 2-23 for more
details).
Actel has arranged all C-cell and R-cell logic modules into
horizontal banks called Clusters. There are two types of
clusters: Type 1 contains two C-cells and one R-cell, while
Type 2 contains one C-cell and two R-cells.
To increase design efficiency and device performance,
Actel
has
further
organized
these
modules
into
SuperClusters. SuperCluster 1 is a two-wide grouping of
Type 1 clusters. SuperCluster 2 is a two-wide group
containing one Type 1 cluster and one Type 2 cluster.
RTSX-SU devices feature more SuperCluster 1 modules
than SuperCluster 2 modules because designers typically
require significantly more combinatorial logic than flip-
flops (Figure 1-2 on page 1-3).
Figure 1-1 • RTSX-SU Family Interconnect Elements
Silicon Substrate
Metal 4
Metal 3
Metal 2
Metal 1
Amorphous Silicon/
Dielectric Antifuse
Tungsten Plug Via
Tungsten Plug Via
Tungsten Plug Contact
Routing Tracks


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