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A54SX32-CG256 Datasheet(PDF) 7 Page - Actel Corporation |
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A54SX32-CG256 Datasheet(HTML) 7 Page - Actel Corporation |
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7 / 46 page  SX Family FPGAs RadTolerant and HiRel v2.1 1-3 Logic Module Design The SX family architecture has been called a “sea-of- modules” architecture because the entire floor of the device is covered with a grid of logic modules with virtually no chip area lost to interconnect elements or routing (see Figure 1-2). Actel provides two types of logic modules, the register cell (R-cell) and the combinatorial cell (C-cell). The R-cell contains a flip-flop featuring more control signals than in previous Actel architectures, including asynchronous clear, asynchronous preset, and clock enable (using the S0 and S1 lines). The R-cell registers feature programmable clock polarity, selectable on a register-by-register basis (Figure 1-3 on page 1-4). This provides the designer with additional flexibility while allowing mapping of synthesized functions into the SX FPGA. The clock source for the R-cell can be chosen from the hardwired clock or the routed clock. The C-cell implements a range of combinatorial functions with up to five inputs (Figure 1-4 on page 1-4). Inclusion of the DB input and its associated inverter function dramatically increases the number of combinatorial functions that can be implemented in a single module from 800 options in previous architectures to more than 4,000 in the SX architecture. An example of the improved flexibility enabled by the inversion capability is the ability to integrate a three-input exclusive-OR function into a single C-cell. This facilitates construction of nine- bit parity-tree functions with 2 ns propagation delays. At the same time, the C-cell structure is extremely synthesis- friendly, simplifying the overall design and reducing synthesis time. Figure 1-2 • Channeled Array and Sea-of-Modules Architectures Channeled Array Architecture Sea-of-Modules Architecture |
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