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A40MX02-PL208A Datasheet(PDF) 5 Page - Actel Corporation |
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A40MX02-PL208A Datasheet(HTML) 5 Page - Actel Corporation |
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5 / 78 page  40MX and 42MX Automotive FPGA Families v3.1 1-1 40MX and 42MX Automotive FPGA Families General Description Actels' automotive-grade MX families provide a high- performance, single-chip solution for shortening the system design and development cycle, offering a cost- effective alternative to ASICs for in-cabin telematics and automobile interconnect applications. The 40MX and 42MX devices are excellent choices for integrating logic that is currently implemented in multiple PALs, CPLDs, and FPGAs. The MX device architecture is based on Actel’s patented antifuse technology implemented in a 0.45µm triple- metal CMOS process. With capacities ranging from 3,000 to 54,000 system gates, the MX devices are live on power-up and have one-fifth the standby power consumption of comparable FPGAs. Actel’s MX FPGAs provide up to 202 user I/Os and are available in a wide variety of packages and speed grades. The automotive-grade 42MX24 and 42MX36 include system-level features such as IEEE Standard 1149.1 (JTAG) Boundary Scan Testing and fast wide-decode modules. In addition, the A42MX36 device offers dual-port SRAM for implementing fast FIFOs, LIFOs, and temporary data storage. The storage elements can efficiently address applications requiring wide datapath manipulation. MX Architectural Overview The MX devices are composed of fine-grained building blocks that enable fast, efficient logic designs. All devices within these families are composed of logic modules, I/O modules, routing resources and clock networks, which are the building blocks for fast logic designs. In addition, the A42MX36 device contains embedded dual-port SRAM modules, which are optimized for high-speed datapath functions such as FIFOs, LIFOs and scratchpad memory. A42MX24 and A42MX36 also contain wide- decode modules. Logic Modules The 40MX logic module is an eight-input, one-output logic circuit designed to implement a wide range of logic functions with efficient use of interconnect routing resources (Figure 1-1). The logic module can implement the four basic logic functions (NAND, AND, OR and NOR) in gates of two, three, or four inputs. The logic module can also implement a variety of D-latches, exclusivity functions, AND-ORs and OR-ANDs. No dedicated hardwired latches or flip-flops are required in the array; latches and flip- flops can be constructed from logic modules whenever required in the application. The 42MX devices contain three types of logic modules: combinatorial (C-modules), sequential (S-modules) and decode (D-modules). Figure 1-2 illustrates the combinatorial logic module. The S-module, shown in Figure 1-3 on page 1-2, implements the same combinatorial logic function as the C-module while adding a sequential element. The sequential element can be configured as either a D-flip-flop or a transparent latch. The S-module register can be bypassed so that it implements purely combinatorial logic. A42MX24 and A42MX36 devices contain D-modules, which are arranged around the periphery of the device. D-modules contain wide-decode circuitry, providing a fast, wide-input AND function similar to that found in CPLD architectures (Figure 1-4 on page 1-2). The D- module allows A42MX24 and A42MX36 devices to perform wide-decode functions at speeds comparable to CPLDs and PALs. The output of the D-module has a programmable inverter for active HIGH or LOW assertion. The D-module output is hardwired to an output pin, and can also be fed back into the array to be incorporated into other logic. Figure 1-1 • 40MX Logic Module Figure 1-2 • 42MX C-Module Implementation D00 D01 D10 D11 S0 S1 Y A0 B0 A1 B1 |
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