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A500K050-PQ208 Datasheet(PDF) 8 Page - Actel Corporation |
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A500K050-PQ208 Datasheet(HTML) 8 Page - Actel Corporation |
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8 / 72 page  Pr oAS I C ® 500K Fa mily 8 Discontinued – v3.0 Cl ock T r ees One of the main architectural benefits of ProASIC is the set of power and delay friendly global networks. The ProASIC family offers 4 global trees. Each of these trees is based on a network of spines and ribs that reach all the tiles in their regions (Figure 7). This flexible clock tree architecture allows users to map up to 56 different internal/external clocks in an A500K270 device (Table 1). The flexible use of the ProASIC clock spine allows the designer to cope with several design requirements. Users implementing clock resource intensive applications can easily route external or gated internal clocks using global routing spines. Users can also drastically reduce delay penalties and save buffering resources by mapping critical high fanout nets to spines. For design hints on using these features, refer to the Efficient Use of ProASIC Clock Trees application note. Figure 7 • A500K130 Global Routing Resources Table 1 • Number of Clock Spines A500K050 A500K130 A500K180 A500K270 Top Spine Height 24 32 40 56 Tiles in Each Top Spine 768 1,024 1,280 1,792 Bottom Spine Height 32 40 56 64 Tiles in Each Bottom Spine 1,024 1,280 1,792 2,048 Global Clock Networks (Trees) 4 4 4 4 Clock Spines/Tree 6 10 12 14 Total Spines 24 40 48 56 Total Tiles 5,376 12,800 18,432 26,880 PAD RING PAD RING Global Pads Global Pads High Performace Global Network Low Skew Global Networks Global Spine Global Ribs Scope of Spine |
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