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A500K180-FG208I Datasheet(PDF) 11 Page - Actel Corporation |
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A500K180-FG208I Datasheet(HTML) 11 Page - Actel Corporation |
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11 / 72 page  Discontinued – v3.0 11 Pr oAS I C ® 5 00K Fa mily Us er Se cu ri ty The ProASIC 500K devices have read-protect bits that, once programmed, lock the entire programmed contents from being read externally. The user can only reprogram the device using the security key. This protects it from being read back and duplicated. Since programmed data is stored in nonvolatile Flash cells (which act like very small capacitors), rather than in the wiring, physical deconstruction cannot be used to compromise data. That approach would be further hampered by the placement of the flash cells, beneath the four metal layers (whose removal could not be accomplished without disturbing the charge on the floating gate). This is the highest security provided in the industry. For more information, refer to the Design Security for Nonvolatile Flash and Antifuse FPGAs white paper for more information. E m be dde d Memo ry Fl oorp l a n The embedded memory is located across the top of the device (see Figure 1 on page 4) in 256x9 blocks. Depending upon the device, 6 to 28 blocks are available to support a variety of memory configurations. Each block can be programmed as an independent memory or combined (using dedicated memory routing resources) to form larger, more complex memories. E m bed ded Memory Con f i g u r ati ons The embedded memory in the ProASIC 500K family provides great configuration flexibility. While other programmable vendors typically use single port memories that can only be transformed into two-port memories by sacrificing half the memory, each ProASIC block is designed and optimized as a two-port memory (1 read, 1 write). This provides 63k bits of total memory for two-port and single port usage in the A500K270 device. Each memory can be configured as FIFO or SRAM, with independent selection of synchronous or asynchronous read and write ports (Table 3 on page 12). Multiple write ports are not supported. Additional characteristics include programmable flags as well as parity check and generation. Figure 12 and Figure 13 on page 13 show the block diagrams of the basic SRAM and FIFO blocks. These memories are designed to operate up to 133 MHz when operated individually. Each block contains a 256 word deep by 9-bit wide (1 read, 1 write) memory. The memory blocks may be combined in parallel to form wider memories or stacked to form deeper memories (Figure 14 on page 14). This provides optimal bit widths of 9 (1 block), 18, 36, and 72, and optimal depths of 256, 512, 768, and 1024. Refer to the Macro Library Guide for more information. Figure 11 • TAP Controller State Diagram Select-DR- Scan Select-IR- Scan 1 1 00 |
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