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A42MX09-VQ208A Datasheet(PDF) 6 Page - Actel Corporation |
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A42MX09-VQ208A Datasheet(HTML) 6 Page - Actel Corporation |
6 / 78 page 40MX and 42MX Automotive FPGA Families 1- 2 v3.1 Dual-Port SRAM Modules The A42MX36 device contains dual-port SRAM modules, which are arranged in 256-bit blocks and can be configured as 32x8 or 64x4. SRAM modules can be cascaded together to form memory spaces of user- definable width and depth. A block diagram of the A42MX36 dual-port SRAM block is shown in Figure 1-5 on page 1-3. The A42MX36 SRAM modules are true dual-port structures containing independent read and write ports. Each SRAM module contains six bits of read and write addressing (RDAD[5:0] and WRAD[5:0], respectively) for 64x4-bit blocks. When configured in byte mode, the highest order address bits (RDAD5 and WRAD5) are not used. The read and write ports of the SRAM block contain independent clocks (RCLK and WCLK) with programmable polarities offering active HIGH or LOW implementation. The SRAM block contains eight data inputs (WD[7:0]) and eight outputs (RD[7:0]), which are connected to segmented vertical routing tracks. The A42MX36 dual-port SRAM blocks provide an optimal solution for high-speed buffered applications requiring FIFO and LIFO queues. The ACTgen Macro Builder within Actel's Designer software provides capability to quickly design memory functions with the SRAM blocks. Figure 1-3 • 42MX S-Module Implementation Figure 1-4 • A42MX24 and A42MX36 D-Module Implementation CLR Up to 7-Input Function Plus D-Type Flip-Flop with Clear Up to 4-Input Function Plus Latch with Clear D0 D1 S Y D Q GATE CLR OUT Up to 8-Input Function (Same as C-Module) D00 D01 D10 D11 S1 S0 Y OUT Up to 7-Input Function Plus Latch D00 D01 D10 D11 S1 S0 Y OUT GATE D Q D00 D01 D10 D11 S1 S0 Y D Q OUT 7 Inputs Hard-Wire to I/O Feedback to Array Programmable Inverter |
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