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A54SX72A-FG208A Datasheet(PDF) 11 Page - Actel Corporation |
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A54SX72A-FG208A Datasheet(HTML) 11 Page - Actel Corporation |
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11 / 68 page  v2.2 1-7 Other Architectural Features Technology The automotive-grade SX-A devices are implemented on a high-voltage, twin-well CMOS process using 0.22 µ design rules. The metal-to-metal antifuse is comprised of a combination of amorphous silicon and dielectric material with barrier metals and has a programmed (“on” state) resistance of 25 Ω with capacitance of 1.0 fF for low signal impedance. Performance The combination of architectural features described above enables automotive-grade SX-A devices to operate with internal clock frequencies of 250 MHz, enabling fast execution of even complex logic functions at extended tempetature ranges. Thus, the automotive- grade SX-A devices are an optimal platform upon which to integrate the functionality previously contained in multiple CPLDs. In addition, designs that previously would have required a gate array to meet performance goals can be integrated into an SX-A device with dramatic improvements in cost and time-to-market. Using timing-driven place-and-route tools, designers can achieve highly deterministic device performance. User Security The Actel FuseLock advantage ensures that unauthorized users will not be able to read back the contents of an Actel antifuse FPGA. In addition to the inherent strengths of the architecture, special security fuses that prevent internal probing and overwriting are hidden throughout the fabric of the device. They are located such that they cannot be accessed or bypassed without destroying the rest of the device, making both invasive and more-subtle noninvasive attacks ineffective against Actel antifuse FPGAs. Look for this symbol to ensure your valuable IP is secure. For more information, refer to Actel’s Implementation of Security in Actel Antifuse FPGAs application note. I/O Modules Each user I/O on an automotive-grade SX-A device can be configured as an input, an output, a tristate output, or a bidirectional pin. I/O pins can be set for 2.5 V or 3.3 V operation through VCCI. SX-A I/Os, combined with array registers, can achieve clock-to-output-pad timing of 5.6 ns even without the dedicated I/O registers. In most FPGAs, I/O cells that have embedded latches and flip- flops require instantiation in HDL code; this is a design complication not encountered in SX-A FPGAs. Fast pin- to-pin timing ensures that the device is able to interface with any other device in the system, which in turn enables parallel design of system components and reduces overall design time. All unused I/Os are configured as tristate outputs by Actel’s Designer software, for maximum flexibility when designing new boards or migrating existing designs. SX-A inputs should be driven by high-speed push-pull devices with a low-resistance pull-up device. If the input voltage is greater than VCCI and a fast push-pull device is NOT used, the high-resistance pull-up of the driver and the internal circuitry of the SX-A I/O may create a voltage divider. This voltage divider could pull the input voltage below specification for some devices connected to the driver. A logic '1' may not be correctly presented in this case. For example, if an open drain driver is used with a pull-up resistor to 3.3V to provide the logic '1' input, and VCCI is set to 2.5 V on the SX-A device, the input signal may be pulled down by the SX-A input. Each I/O module has an available power-up resistor of approximately 50 k Ω that can configure the I/O in a known state during power-up. Just slightly before VCCA reaches 2.5 V, the resistors are disabled, so the I/Os will be controlled by user logic. See Table 1-2 on page 1-8 and Table 1-3 on page 1-8 for more information concerning available I/O features. Hot Swapping During power-up/down (or partial up/down), all I/Os are tristated. VCCA and VCCI do not have to be stable during power-up/down. After the SX-A device is plugged into an electrically active system, the device will not degrade the reliability of or cause damage to the host system. The device’s output pins are driven to a high impedance state until normal chip operating conditions are reached. Table 1-4 on page 1-8 summarizes the VCCA voltage at which the I/Os behave according to the user’s design for an SX-A device at room temperature for various ramp-up rates. The data reported assumes a linear ramp-up profile to 2.5V. For more information on power-up and hot-swapping, refer to the application note, Actel SX-A and RT54SX-S Devices in Hot-Swap and Cold-Sparing Applications. ™ e u |
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