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A3PE1500-FFGG896PP Datasheet(PDF) 2 Page - Actel Corporation |
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A3PE1500-FFGG896PP Datasheet(HTML) 2 Page - Actel Corporation |
2 / 152 page II v1.0 I/Os Per Package1 ProASIC3E Devices A3PE600 A3PE1500 3 A3PE3000 3 Cortex-M1 Devices2 M1A3PE1500 M1A3PE3000 Package I/O Types PQ208 147 65 147 65 147 65 FG256 165 79 –––– FG324 – – – – 221 110 FG484 270 135 280 139 341 168 FG676 – – 444 222 – – FG896 – – – – 620 310 Notes: 1. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3E Flash Family FPGAs handbook to ensure compliance with design and board migration requirements. 2. Each used differential I/O pair reduces the number of single-ended I/Os available by two. 3. For A3PE1500 and A3PE3000 devices, the usage of certain I/O standards is limited as follows: – SSTL3(I) and (II): up to 40 I/Os per north or south bank – LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank – SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank 4. FG256 and FG484 are footprint-compatible packages. 5. When using voltage-referenced I/O standards, one I/O pin should be assigned as a voltage-referenced pin (VREF) per minibank (group of I/Os). 6. "G" indicates RoHS-compliant packages. Refer to the "ProASIC3E Ordering Information" on page III for the location of the "G" in the part number. |
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