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M1A3PE1500-FFGG896ES Datasheet(PDF) 10 Page - Actel Corporation |
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M1A3PE1500-FFGG896ES Datasheet(HTML) 10 Page - Actel Corporation |
10 / 152 page ProASIC3E Device Family Overview 1- 6 v1.0 Pro I/Os with Advanced I/O Standards The ProASIC3E family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V). ProASIC3E FPGAs support 19 different I/O standards, including single- ended, differential, and voltage-referenced. The I/Os are organized into banks, with eight banks per device (two per side). The configuration of these banks determines the I/O standards supported. Each I/O bank is subdivided into VREF minibanks, which are used by voltage-referenced I/Os. VREF minibanks contain 8 to 18 I/Os. All the I/Os in a given minibank share a common VREF line. Therefore, if any I/O in a given VREF minibank is configured as a VREF pin, the remaining I/Os in that minibank will be able to use that reference voltage. Each I/O module contains several input, output, and enable registers. These registers allow the implementation of the following: • Single-Data-Rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II) • Double-Data-Rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II) ProASIC3E banks support M-LVDS with 20 multi-drop points. Part Number and Revision Date Part Number 51700098-001-1 Revised March 2008 List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version Changes in Current Version (v1.0) Page 51700098-001-1 This document was divided into two sections and given a version number, starting at v1.0. The first section of the document includes features, benefits, ordering information, and temperature and speed grade offerings. The second section is a device family overview. N/A 51700098-001-0 (January 2008) The FG324 package was added to the "ProASIC3E Product Family" table, the "I/Os Per Package1" table, and the "Temperature Grade Offerings" table for A3PE3000. I, II, IV v2.1 (July 2007) This document was previously in datasheet v2.1. As a result of moving to the handbook format, Actel has restarted the version numbers. The new version number is 51700098-001-0. N/A v2.0 (April 2007) CoreMP7 information was removed from the "Features and Benefits" section. i The M1 device part numbers have been updated in Table 4 • ProASIC3E Product Family, "Packaging Tables", "Temperature Grade Offerings", "Speed Grade and Temperature Grade Matrix", and "Speed Grade and Temperature Grade Matrix". iii, ii, iii, iv, iv The words "ambient temperature" were added to the temperature range in the "Temperature Grade Offerings", "Speed Grade and Temperature Grade Matrix", and "Speed Grade and Temperature Grade Matrix" sections. iii, iv, iv The "Clock Conditioning Circuit (CCC) and PLL" section was updated. i Advance v0.6 (January 2007) In the "Temperature Grade Offerings" section, Ambient was deleted. iii Ambient was deleted from "Temperature Grade Offerings". iii Ambient was deleted from the "Speed Grade and Temperature Grade Matrix". iv |
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