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A32300DXV-1PGB Datasheet(PDF) 8 Page - Actel Corporation |
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A32300DXV-1PGB Datasheet(HTML) 8 Page - Actel Corporation |
8 / 84 page Inte gra t or Serie s FP GAs: 1 200XL a nd 3200 DX F amilie s 8 Discontinued – v3.0 such as FIFOs, LIFOs, and RAM arrays. Additionally, unused SRAM blocks can be used to implement registers for other logic within the design. I/O M o du le s The I/O modules provide the interface between the device pins and the logic array. Figure 5 is a block diagram of the I/O module. A variety of user functions, determined by a library macro selection, can be implemented in the module (refer to the Macro Library Guide for more information). I/O modules contain a tri-state buffer, input and output latches which can be configured for input, output, or bi-directional pins (Figure 5). Figure 5 • I/O Module G/CLK* QD EN PAD * Can be Configured as a Latch or D Flip-Flop From Array To Array (Using C-Module) G/CLK* QD The Integrator Series devices contain flexible I/O structures where each output pin has a dedicated output enable control. The I/O module can be used to latch input and/or output data, providing a fast set-up time. In addition, the Actel Designer Series software tools can build a D-type flip-flop using a C-module to register input and/or output signals. Actel’s Designer Series development tools provide a design library of I/O macrofunctions which can implement all I/O configurations supported by the Integrator Series FPGAs. Ro ut in g Stru ctu r e The Integrator Series architecture uses vertical and horizontal routing tracks to interconnect the various logic and I/O modules. These routing tracks are metal interconnects that may either be of continuous length or broken into pieces called segments. Varying segment lengths allows interconnection of over 90% of design tracks to occur with only two antifuse connections. Segments can be joined together at the ends using antifuses to increase their lengths up to the full length of the track. All interconnects can be accomplished with a maximum of four antifuses. Horizontal Routing Horizontal channels are located between the rows of modules and are composed of several routing tracks. The horizontal routing tracks within the channel are divided into one or more segments. The minimum horizontal segment length is the width of a module pair, and the maximum horizontal segment length is the full length of the channel. Any segment that spans more than one-third the row length is considered a long horizontal segment. A typical channel is shown in Figure 6. Non-dedicated horizontal routing tracks are used to route signal nets; dedicated routing tracks are used for the global clock networks and for power and ground tie-off tracks. Vertical Routing Another set of routing tracks run vertically through the module. Vertical tracks are of three types: input, output, and long, and are divided into one or more segments. Each segment in an input track is dedicated to the input of a particular module; each segment in an output track is dedicated to the output of a particular module. Long segments are uncommitted and can be assigned during routing. Each output segment spans four channels (two above and two below), except near the top and bottom of the array where edge effects occur. Long Vertical Tracks contain either one or two segments. An example of vertical routing tracks and segments is shown in Figure 6. Figure 6 • Routing Structure Vertical Routing Tracks Antifuses Logic Segmented Horizontal Routing Tracks Modules Antif u se St ructure An antifuse is a “normally open” structure as opposed to the normally closed fuse structure used in PROMs or PALs. The use of antifuses to implement a programmable logic device results in highly-testable structures as well as efficient |
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