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APA750-FLGES Datasheet(PDF) 8 Page - Actel Corporation

Part # APA750-FLGES
Description  ProASIC Flash Family FPGAs
Download  174 Pages
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Manufacturer  ACTEL [Actel Corporation]
Direct Link  http://www.actel.com
Logo ACTEL - Actel Corporation

APA750-FLGES Datasheet(HTML) 8 Page - Actel Corporation

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ProASICPLUS Flash Family FPGAs
1- 2
v5.7
ProASICPLUS Architecture
The
proprietary
ProASICPLUS
architecture
provides
granularity comparable to gate arrays.
The ProASICPLUS device core consists of a Sea-of-Tiles
(Figure 1-1). Each tile can be configured as a three-input
logic function (e.g., NAND gate, D-Flip-Flop, etc.) by
programming
the
appropriate
Flash
switch
interconnections (Figure 1-2 and Figure 1-3 on page 1-3).
Tiles and larger functions are connected with any of the
four levels of routing hierarchy. Flash switches are
distributed
throughout
the
device
to
provide
nonvolatile, reconfigurable interconnect programming.
Flash switches are programmed to connect signal lines to
the appropriate logic cell inputs and outputs. Dedicated
high-performance lines are connected as needed for fast,
low-skew global signal distribution throughout the core.
Maximum core utilization is possible for virtually any
design.
ProASICPLUS devices also contain embedded, two-port
SRAM blocks with built-in FIFO/RAM control logic.
Programming
options
include
synchronous
or
asynchronous operation, two-port RAM configurations,
user defined depth and width, and parity generation or
checking.
Please
see
the
"Embedded
Memory
Configurations"
section
on
page 1-22
for
more
information.
Figure 1-1 • The ProASICPLUS Device Architecture
Figure 1-2 • Flash Switch
256x9 Two-Port SRAM
or FIFO Block
Logic Tile
256x9 Two Port SRAM
or FIFO Block
RAM Block
RAM Block
I/Os
Sensing
Switching
Switch In
Switch Out
Word
Floating Gate


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