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LTC1408IUH-12 Datasheet(PDF) 1 Page - Linear Technology |
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LTC1408IUH-12 Datasheet(HTML) 1 Page - Linear Technology |
1 / 20 page 1 LTC1408-12 140812f 6 Channel, 12-Bit, 600ksps Simultaneous Sampling ADC with Shutdown The LTC ®1408-12 is a 12-bit, 600ksps ADC with six simultaneously sampled differential inputs. The device draws only 5mA from a single 3V supply, and comes in a tiny 32 pin (5mm × 5mm) QFN package. A SLEEP shut- down feature further reduces power consumption to 6 µW. The combination of low power and tiny package makes the LTC1408-12 suitable for portable applications. The LTC1408-12 contains six separate differential inputs that are sampled simultaneously on the rising edge of the CONV signal. These six sampled inputs are then converted at a rate of 100ksps per channel. The 83dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. The device converts 0V to 2.5V unipolar inputs differen- tially, or ±1.25V bipolar inputs also differentially, depending on the state of the BIP pin. Any analog input may swing rail-to-rail as long as the differential input range is maintained. The conversion sequence can be abbreviated to convert fewer than six channels, depending on the logic state of the SEL2, SEL1 and SEL0 inputs. The serial interface sends out the six conversion results in 96 clocks for compatibility with standard serial interfaces. ■ 600ksps ADC with 6 Simultaneously Sampled Differential Inputs ■ 100ksps Throughput per Channel ■ 72dB SINAD ■ Low Power Dissipation: 15mW ■ 3V Single Supply Operation ■ 2.5V Internal Bandgap Reference, Can be Overdriven with External Reference ■ 3-Wire SPI-Compatible Serial Interface ■ 0V to 2.5V Unipolar, or ±1.25V Bipolar Differential Input Range ■ SLEEP (6 µW) Shutdown Mode ■ NAP (3.3mW) Shutdown Mode ■ Internal Conversion Triggered by CONV ■ 83dB Common Mode Rejection ■ Tiny 32-Pin (5mm ××××× 5mm) QFN Package ■ Multiphase Power Measurement ■ Multiphase Motor Control ■ Data Acquisition Systems ■ Uninterruptable Power Supplies APPLICATIO S FEATURES DESCRIPTIO BLOCK DIAGRA – 4 5 25 24 – 7 6 9 12 13 16 19 8 CH0– CH0+ CH1– CH1+ 10 11 – 14 15 CH2– CH2+ CH3– CH3+ – 17 18 – 20 21 S AND H S AND H S AND H S AND H S AND H CH4– CH4+ CH5– CH5+ MUX VREF 10 µF BIP SEL2 SEL1 SEL0 GND 2.5V REFERENCE 600ksps 12-BIT ADC 12-BIT LATCH 5 12-BIT LATCH 4 12-BIT LATCH 3 12-BIT LATCH 2 12-BIT LATCH 1 12-BIT LATCH 0 10 µF3V VCC VDD 26 29 23 22 33 27 28 2 1 SD0 0.1 µF 3 OVDD 3V 32 SCK 31 DGND OGND 30 CONV THREE- STATE SERIAL OUTPUT PORT TIMING LOGIC 235114 TA01 – S AND H , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 6084440, 6522187. |
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