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LTC4264 Datasheet(PDF) 3 Page - Linear Technology |
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LTC4264 Datasheet(HTML) 3 Page - Linear Technology |
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3 / 24 page  LTC4264 3 4264f Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltages are with respect to GND pin unless otherwise noted. Note 3: Active high PWRGD pin internal clamp circuit self-regulates to 14V with respect to VOUT. Note 4: The LTC4264 operates with a negative supply voltage in the range of –1.5V to –57V. To avoid confusion, voltages in this data sheet are referred to in terms of absolute magnitude. Note 5: In IEEE 802.3af systems, the maximum voltage at the PD jack is defined to be –57V. See Applications Information. Note 6: The LTC4264 is designed to work with two polarity protection diodes in series with the input. Parameter ranges specified in the Electrical Characteristics are with respect to LTC4264 pins and are designed to meet IEEE 802.3af specifications when the drop from the two diodes is included. See Applications Information. Note 7: Signature resistance is measured via the two-point ΔV/ΔI method as defined by IEEE 802.3af. The LTC4264 signature resistance is offset from 25k to account for diode resistance. With two series diodes, the total PD resistance will be between 23.75k and 26.25k and meet IEEE 802.3af specifications. The minimum probe voltages measured at the LTC4264 pins are – 1.5V and – 2.5V. The maximum probe voltages are –9.1V and –10.1V. Note 8: The LTC4264 includes hysteresis in the UVLO voltages to preclude any start-up oscillation. Per IEEE 802.3af requirements, the LTC4264 will power up from a voltage source with 20 Ω series resistance on the first trial. Note 9: IIN_CLASS does not include classification current programmed at Pin 3. Total supply current in classification mode will be IIN_CLASS + ICLASS (see Note 10). Note 10: ICLASS is the measured current flowing through RCLASS. ΔICLASS accuracy is with respect to the ideal current defined as ICLASS = 1.237/RCLASS. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIL_ILIM ILIM_EN Low Level Input Voltage With Respect to VIN (Note 13) ● 1V VPWRGD_OUT Active Low Power Good Output Low Voltage IPWRGD = 1mA, VIN = –54V, ⎯P⎯W⎯R⎯G⎯D Referenced to VIN ● 0.5 V IPWRGD_LEAK Active Low Power Good Leakage VIN = 0V, VPWRGD = 57V ● 1µA VPWRGD_OUT Active High Power Good Output Low Voltage IPWRGD = 0.5mA, VIN = –52V, VOUT = –4V, PWRGD Referenced to VOUT (Note 14) ● 0.35 V VPWRGD_VCLAMP Active High Power Good Voltage-Limiting Clamp IPWRGD = 2mA, VOUT = 0V, With Respect to VOUT (Note 3) ● 12.0 14.0 16.5 V IPWRGD_LEAK Active High Power Good Leakage VPWRGD = 11V, with Respect to VOUT, VOUT = VIN = –54V ● 1µA RON On Resistance I = 700mA, VIN = –54V Measured from VIN to VOUT (Note 11) ● 0.5 0.6 0.8 Ω Ω IOUT_LEAK VOUT Leakage VIN = –57V, GND = SHDN = VOUT = 0V ● 1µA ILIMIT_HIGH Input Current Limit During Normal Operation VIN = –54V, VOUT = –53V, ILIM_EN Floating (Notes 15, 16) ● 700 750 800 mA ILIMIT_LOW Inrush Current Limit VIN = –54V, VOUT = –53V (Notes 15, 16) ● 250 300 350 mA ILIMIT_DISA Safeguard Current Limit when ILIMIT_HIGH Disabled VIN = –54V, VOUT = –52.5V, ILIM_EN Tied to VIN (Notes 15, 16, 17) 1.20 1.45 1.65 A ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) tCLASSRDY is the time for ICLASS to settle to within ±3.5% of ideal. The current accuracy specification does not include variations in RCLASS resistance. The total classification current for a PD also includes the IC quiescent current (IIN_CLASS). See Applications Information. Note 11: This parameter is assured by design and wafer level testing. Note 12: To disable the 25k signature, tie SHDN to GND (±0.1V) or hold SHDN pin high with respect to VIN. See Applications Information. Note13: ILIM_EN pin is pulled high internally and for normal operation should be left floating. To disable high level current limit, tie ILIM_EN to VIN. See Applications Information. Note 14: Active high power good is referenced to VOUT and is valid for GND-VOUT ≥ 4V. Measured at –52V due to test hardware limitations. Note 15: The LTC4264 includes a dual current limit. At turn-on, before C1 is charged, the LTC4264 current level is set to ILIMIT_LOW. After C1 is charged and with ILIM_EN floating, the LTC4264 switches to ILIMIT_HIGH. With ILIM_EN pin tied low, the LTC4264 switches to ILIMIT_DISA. The LTC4264 stays in ILIMIT_HIGH or ILIMIT_DISA until the input voltage drops below the UVLO turn- off threshold or a thermal overload occurs. Note 16: The LTC4264 features thermal overload protection. In the event of an overtemperature condition, the LTC4264 will turn off the power MOSFET, disable the classification load current and present an invalid power good signal. Once the LTC4264 cools below the overtemperature limit, the LTC4264 current limit switches to ILIMIT_LOW and normal operation resumes. Thermal overload protection is intended to protect the device during momentary fault conditions and continuous operation in thermal overload should be avoided as it may impair device reliability. Note 17: ILIMIT_DISA is a safeguard current limit that is activated when the normal input current limit (ILIMIT_HIGH) is defeated using the ILIM_EN pin. Currents at or near ILIMIT_DISA will cause significant package heating and may require a reduced maximum ambient operating temperature in order to avoid tripping the thermal overload protection. See Applications Information. |
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