8

LTC1860L/LTC1861L

18601Lf

SDO

3k

20pF

TEST POINT

1860 TC01

SCK

SDO

1860 TC02

1860 TC03

CONV

SDO

SDO

1860 TC04

TEST CIRCUITS

SDO

WAVEFORM 1

(SEE NOTE 1)

90%

10%

SDO

WAVEFORM 2

(SEE NOTE 2)

CONV

NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH

THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL

NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH

THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL

1860 TC05

LTC1860L OPERATION

Operating Sequence

The LTC1860L conversion cycle begins with the rising

sion is finished. If CONV is left high after this time, the

LTC1860L goes into sleep mode drawing only leakage

current. On the falling edge of CONV, the LTC1860L goes

into sample mode and SDO is enabled. SCK synchronizes

the data transfer with each bit being transmitted from SDO

on the falling SCK edge. The receiving system should

capture the data from SDO on the rising edge of SCK. After

completing the data transfer, if further SCK clocks are

applied with CONV low, SDO will output zeros indefinitely.

See Figure 1.

Analog Inputs

The LTC1860L has a unipolar differential analog input. The

Reference Input

The voltage on the reference input of the LTC1860L (and

the LTC1861L MSOP package) defines the full-scale range

of the A/D converter. These ADCs can operate with refer-

APPLICATIO S I FOR ATIO