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LTC1757A-1EMS8 Datasheet(PDF) 11 Page - Linear Technology |
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LTC1757A-1EMS8 Datasheet(HTML) 11 Page - Linear Technology |
11 / 16 page 11 LTC1757A-1/LTC1757A-2 External pole frequencies within the loop may further reduce phase margin. The phase margin degradation, due to external and internal pole combinations, is difficult to determine since complex poles are present. Gain peaking may occur, resulting in higher bandwidth and lower phase margin than predicted from the open loop Bode plot. A low frequency AC SPICE model of the LTC1757A power APPLICATIO S I FOR ATIO controller is included to better determine pole and zero interactions. The user can apply external gains and poles to determine bandwidth and phase margin. DC, transient and RF information cannot be extracted from the present model. The model is suitable for external gain evaluations up to 6 ×. The 1.25MHz PCTL input filter limits the band- width, therefore, the RF input is used in the model. Figure 5. Closed Loop Block Diagram Figure 6. SPICE Model Open Loop Gain and Phase Characteristics from RF to VPCA Figure 7. SPICE Model Closed Loop Voltage Gain FREQUENCY (Hz) 100 –20 –10 0 20 10 40 30 1k 10k 100k 1M 10M 1757A F04 –30 –40 –50 –60 60 50 80 70 –20 0 20 60 40 100 80 –40 –60 –80 –100 140 120 180 160 PHASE GAIN RLOAD = 2k CLOAD = 33pF Figure 4. Measured Open Loop Gain and Phase G1 PCTL IFB G2 H1 RF 1757A F05 H2 VPCA/B LTC1757A RF DETECTOR CONTROL AMPLIFER BW1 ≅ 400kHz RF POWER AMP CONTROLLED RF OUTPUT POWER DIRECTIONAL COUPLER 14dB to 20dB LOSS + – FREQUENCY (Hz) 0 –20 40 80 20 60 100 1k 10k 100k 1M 10M 1757A F06 –40 –100 –50 0 50 100 150 200 PHASE GAIN CLOAD = 33pF RLOAD = 2k FREQUENCY (Hz) 100 1k 10k 100k 1M 10M 1757A F07 –15 –20 –25 –10 –5 0 5 EXTERNAL GAIN = 3 CLOAD = 33pF RLOAD = 2k BANDWIDTH = 1.35MHz |
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