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LTC1760CFW Datasheet(PDF) 6 Page - Linear Technology |
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LTC1760CFW Datasheet(HTML) 6 Page - Linear Technology |
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6 / 44 page  LTC1760 6 1760f ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDCIN = 20V, VBAT1 = 12V, VBAT2 = 12V, VVDDS = 3.3V, VVCC2 = 5.2V unless otherwise noted. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2. Battery voltage must be adequate to drive gates of power path P-channel FET switches. This does not affect charging voltage of the battery, which can be zero volts during wake-up charging. Note 3. DCIN, BAT1, BAT2 are held at 12V and GDCI, GB1I, GB2I are forced to 10.5V. SCP is set at 12V to measure source current at GDCI, GB1I and GB2I. SCP is set at 11.9V to measure sink current at GDCI, GB1I and GB2I. Note 4. Extrapolated from testing with CL = 50pF. Note 5. Accuracy dependent upon external sense resistor and compensation components. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Note 6. The LTC1760C is guaranteed to meet specified performance from 0°C to 70°C and is designed, characterized and expected to meet specified performance at –40°C and 85°C, but is not tested at these extended temperature limits. Note 7. Charger servos to the value reported by a Voltage() query. This is the internal cell voltage measured by the battery electronics and may be lower than the terminal voltage. See “Operation Section 3.6” for more information. Note 8. CLOAD is the combined capacitance on the host’s SMBus connection and the selected battery’s SMBus connection. Note 9. CLOAD_MAX is the maximum allowed combined capacitance on THxA, THxB and the battery’s SafetySignalx connections. SCL/SCL1/SCL2/SDA/SDA1/ SDA2/ VVCC2 = 0V, VVDDS = 0V, ● 2uA SMBALERT Power Down Leakage VSCL, VSCL1, VSCL2, VSDA, VSDA1, VSDA2, VSMBALERT = 5.5V SMBALERT Output Low Voltage (VOL)IPULLUP = 500µA ● 0.4 V SMBALERT Output Pull-Up Current VSMBALERT = 0.4V 3.5 10 17.5 µA VIL_VDDS VDDS Input Low Voltage (VIL) ● 1.5 V VIH_VDDS VDDS Input High Voltage (VIH) ● 2.6 V VDDS Operating Voltage ● 3 5.5 V VDDS Operating Current VSCL, VSDA = VVDDS , VVDDS = 5V 18 µA VIL_MODE MODE Input Low Voltage (VIL)VVCC2 = 4.85V ● VVCC2 • 0.3 V VIH_MODE MODE Input High Voltage (VIH)VVCC2 = 4.85V ● VVCC2 • 0.7 V MODE Input Current (IIH) MODE = VVCC2 • 0.7V, VVCC2 = 4.85V ● –1 1 µA MODE Input Current (IIL) MODE = VVCC2 • 0.3V, VVCC2 = 4.85V ● –1 1 µA Charger Timing tTIMEOUT Timeout for Wake-Up Charging and ● 140 175 210 sec Controlled Charging tQUERY Sampling Rate Used by the LTC1760 to 1 sec Update Charging Parameters SMBus Timing SCL Serial-Clock High Period(tHIGH) At IPULLUP = 350µA, CLOAD = 150pF (Note 8) ● 4 µs SCL Serial-Clock Low Period (tLOW) At IPULLUP = 350µA, CLOAD = 150pF (Note 8) ● 4.7 µs SDA/SCL Rise Time (tr)CLOAD = 150pF, RPU = 9.31k (Note 8) ● 1000 ns SDA/SCL Fall Time (tf)CLOAD = 150pF, RPU = 9.31k (Note 8) ● 300 ns SMBus Accelerator Trip Voltage Range ● 0.8 1.42 V Start-Condition Setup Time (tSU:STA) ● 4.7 µs Start-Condition Hold Time (tHD:STA) ● 4 µs SDA to SCL Rising-Edge ● 250 ns Setup Time (tSU:DAT) SDA to SCL Falling-Edge Hold Time, ● 300 ns Slave Clocking in Data (tHD:DAT) tTIMEOUT_SMB The LTC1760 will Release the SMBus ● 25 35 ms and Terminate the Current Master or Slave Command if the Command is not Completed Before this Time |
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