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LTC2053 Datasheet(PDF) 9 Page - Linear Technology |
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LTC2053 Datasheet(HTML) 9 Page - Linear Technology |
9 / 16 page LTC2053/LTC2053-SYNC 9 2053syncfb – + ZERO-DRIFT OP AMP CH OUT 2053 BD 4 V– 5 REF 6 RG 8 V+ 1 EN/CLK* 3 +IN 2 –IN CS 7 *NOTE: PIN 1 IS EN ON THE LTC2053 AND CLK ON THE LTC2053-SYNC. EN (Pin 1, LTC2053 Only): Active Low Enable Pin. CLK (Pin 1, LTC2053-SYNC Only): Clock input for synchronizing to external system clock. –IN (Pin 2): Inverting Input. +IN (Pin 3): Noninverting Input. V– (Pin 4): Negative Supply. REF (Pin 5): Voltage Reference (VREF) for Amplifier Output. PI FU CTIO S RG (Pin 6): Inverting Input of Internal Op Amp. With a resistor, R2, connected between the OUT pin and the RG pin and a resistor, R1, between the RG pin and the REF pin, the DC gain is given by 1 + R2 / R1. OUT (Pin 7): Amplifier Output. VOUT = GAIN (V+IN – V–IN) + VREF V+ (Pin 8): Positive Supply. BLOCK DIAGRA APPLICATIO S I FOR ATIO Theory of Operation The LTC2053 uses an internal capacitor (CS) to sample a differential input signal riding on a DC common mode voltage (see Block Diagram). This capacitor’s charge is transferred to a second internal hold capacitor (CH) trans- lating the common mode of the input differential signal to that of the REF pin. The resulting signal is amplified by a zero-drift op amp in the noninverting configuration. The RG pin is the negative input of this op amp and allows external programmability of the DC gain. Simple filtering can be realized by using an external capacitor across the feedback resistor. Input Voltage Range The input common mode voltage range of the LTC2053 is rail-to-rail. However, the following equation limits the size of the differential input voltage: V– ≤ (V+IN – V–IN) + VREF ≤ V+ – 1.3 Where V+IN and V–IN are the voltages of the +IN and –IN pins respectively, VREF is the voltage at the REF pin and V+ is the positive supply voltage. For example, with a 3V single supply and a 0V to 100mV differential input voltage, VREF must be between 0V and 1.6V. ±5 Volt Operation When using the LTC2053 with supplies over 5.5V, care must be taken to limit the maximum difference between any of the input pins (+IN or –IN) and the REF pin to 5.5V; if not, the device will be damaged. For example, if rail-to- rail input operation is desired when the supplies are at ±5V, the REF pin should be 0V, ±0.5V. As a second example, if V+ is 10V and V– and REF are at 0V, the inputs should not exceed 5.5V. |
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