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AK2300 Datasheet(PDF) 4 Page - Asahi Kasei Microsystems |
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AK2300 Datasheet(HTML) 4 Page - Asahi Kasei Microsystems |
4 / 19 page [ AK2300] <MS0998-E-00> 4 2008/9 PIN FUNCTION Pin types DIN: Digital input DOUT: Digital output PWR: Power / Ground AIN: Analog input AOUT: Analog output Pin# Name Type Function 7 VFTN AIN Negative analog onput of analog input OP amp. Signgle-end amplifire is composed the exernal registers. Transmit gain is defined by the ratio of the external registers. 6 GST AOUT Output of the transmit OP amp. The external feedback resister is connected between this pin and VFTN. 4 VR AOUT Analog output of the D/A converter equivalent to the received PCM code. 14 FS DIN Frame sync input This clock is input for the internal PLL which generates the internal system clocks. FS must be 8kHz clock which synchronized with BCLK. 5 BCLK DIN Bit clock of PCM data interface This clock defines the input/output timing of DX and RX. The frequency of BCLK should be 64kHz ´ N (N=1~32) and duty should be 40~60%. When this pin is taken low, power down the device. *Please don’t stop BCLK at “H” level. 11 DX DOUT Serial output of PCM data The PCM data is synchronized with BCLK. This output remains in the low level except for the period in which PCM data is transmitted. 16 DR DIN Serial input of PCM data The PCM data is synchronized with BCLK. 1 MUTEN DIN Mute setting pin “L” level forces both A/D, D/A output to mute state. 2 PDN DIN Power down setting pin “L” level forces power down mode. 13 DIF0 DIN Audio data interface select pin ”L”=A-law,”H”=m-law,“FS”=Linear PCM (Please connect DIF0 with FS(#14) at a Linear PCM mode.) 5 DIF1 DIN Audio data interface timing select pin “H” : MSB of DX/DR are input/output by rising edge of FS.(Connect to VDD) “L” : MSB of DX/DR are input/output by next rising edge of BCLK after the rising edge of FS. (Please connect it with VDD when DIF1 is “H”.) 3 VDD PWR Positive supply voltage 12 LVDD PWR Positive supply voltage for digital interface 10 VSS PWR Ground (0V) 8 VREF AOUT Analog reference voltage output External capacitance (0.1 mF) should be connected between this pin and VSS. Please do not connect external load to this pin. 9 PLLC AOUT PLL loop filter output External capacitance (0.056 mF±30%: Includes temperature characteristic) should be connected between this pin and VSS. Exposed Pad - Flip side PAD VSS or Open |
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