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LTC2361CS6-TRPBF Datasheet(PDF) 9 Page - Linear Technology |
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LTC2361CS6-TRPBF Datasheet(HTML) 9 Page - Linear Technology |
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9 / 20 page  LTC2360/LTC2361/LTC2362 9 236012f PIN FUNCTIONS S6 Package VDD (Pin 1): Positive Supply. The VDD range is 2.35V to 3.6V. VDD also defines the input span of the ADC, 0V to VDD. Bypass to GND and to a solid ground plane with a 2.2μF ceramic capacitor (or 2.2μF tantalum in parallel with 0.1μF ceramic). GND (Pin 2): Ground. The GND pin must be tied directly to a solid ground plane. AIN (Pin 3): Analog Input. AIN is a single-ended input with respect to GND with a range from 0V to VDD. SCK (Pin 4): Shift Clock Input. The SCK serial clock syn- chronizes the serial data transfer. SDO data transitions on the falling edge of SCK. SDO (Pin 5): Three-State Serial Data Output. The A/D conversion result is shifted out on SDO as a serial data stream with MSB first. The data stream consists of 12 bits of conversion data followed by trailing zeros. CONV (Pin 6): Convert Input. This active high signal starts a conversion on the rising edge. The device automatically powers down after conversion. A logic low on this input enables the SDO pin, allowing the data to be shifted out. TS8 Package VDD (Pin 1): Positive Supply. The VDD range is 2.35V to 3.6V. Bypass to GND and to a solid ground plane with a 2.2μF ceramic capacitor (or 2.2μF tantalum in parallel with 0.1μF ceramic). VREF (Pin 2): Reference Input. VREF defines the input span of the ADC, 0V to VREF. The VREF range is 1.4V to VDD. Bypass to GND and to a solid ground plane with a 2.2μF ceramic capacitor (or 2.2μF tantalum in parallel with 0.1μF ceramic). GND (Pin 3): Ground. The GND pin must be tied directly to a solid ground plane. AIN (Pin 4): Analog Input. AIN is a single-ended input with respect to GND with a range from 0V to VREF. OVDD (Pin 5): Output Driver Supply for SDO. The OVDD range is 1V to 3.6V. Bypass to GND and to a solid ground plane with a 2.2μF ceramic capacitor (or 2.2μF tantalum in parallel with 0.1μF ceramic). OVDD can be driven separately from VDD and OVDD can be higher than VDD. SDO (Pin 6): Three-State Serial Data Output. The A/D conversion result is shifted out on SDO as a serial data stream with MSB first. The data stream consists of 12 bits of conversion data followed by trailing zeros. SCK (Pin 7): Shift Clock Input. The SCK serial clock syn- chronizes the serial data transfer. SDO data transitions on the falling edge of SCK. CONV (Pin 8): Convert Input. This active high signal starts a conversion on the rising edge. The device automatically powers down after conversion. A logic low on this input enables the SDO pin, allowing the data to be shifted out. |
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