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LTC2433-1CMS Datasheet(PDF) 6 Page - Linear Technology |
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LTC2433-1CMS Datasheet(HTML) 6 Page - Linear Technology |
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6 / 28 page  LTC2433-1 6 24331fa VCC (Pin 1): Positive Supply Voltage. Bypass to GND with a 10 µF tantalum capacitor in parallel with 0.1µF ceramic capacitor as close to the part as possible. REF+ (Pin 2), REF– (Pin 3): Differential Reference Input. The voltage on these pins can have any value between GND and VCC as long as the reference positive input, REF+, is maintained more positive than the reference negative input, REF –, by at least 0.1V. IN+ (Pin 4), IN– (Pin 5): Differential Analog Input. The voltage on these analog inputs can have any value between GND and VCC. Within these limits the converter bipolar input range (VIN = IN+ – IN–) extends from – 0.5 • (VREF) to 0.5 • (VREF). Outside this input range the converter produces unique overrange and underrange output codes. GND (Pin 6): Ground. Connect this pin to a ground plane through a low impedance connection. CS (Pin 7): Active LOW Digital Input. A LOW on this pin enables the SDO digital output and wakes up the ADC. Following each conversion the ADC automatically enters the Sleep mode and remains in this low power state as long as CS is HIGH. A LOW-to-HIGH transition on CS during the Data Output transfer aborts the data transfer and starts a new conversion. SDO (Pin 8): Three-State Digital Output. During the Data Output period, this pin is used as serial data output. When the chip select CS is HIGH (CS = VCC) the SDO pin is in a high impedance state. During the Conversion and Sleep periods, this pin is used as the conversion status output. The conversion status can be observed by pulling CS LOW. SCK (Pin 9): Bidirectional Digital Clock Pin. In Internal Serial Clock Operation mode, SCK is used as digital output for the internal serial interface clock during the Data Output period. In External Serial Clock Operation mode, SCK is used as digital input for the external serial interface clock during the Data Output period. A weak internal pull- up is automatically activated in Internal Serial Clock Op- eration mode. The Serial Clock Operation mode is deter- mined by the logic level applied to the SCK pin at power up or during the most recent falling edge of CS. FO (Pin 10): Frequency Control Pin. Digital input that controls the ADC’s notch frequencies and conversion time. When the FO pin is connected to GND (FO = 0V), the converter uses its internal oscillator and rejects 50Hz and 60Hz simultaneously. When FO is driven by an external clock signal with a frequency fEOSC, the converter uses this signal as its system clock and the digital filter has 87dB minimum rejection in the range fEOSC/2560 ±14% and 110dB minimum rejection at fEOSC/2560 ±4%. PI FU CTIO S |
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